From ee4b38dce378407f4b8dc5e7b37d334ec3335fa4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 12 Mar 2022 00:46:11 -0600
Subject: [PATCH] dtim writes are supressed on non cacheable operation.

---
 pipelined/src/ifu/ifu.sv  |  2 +-
 pipelined/src/lsu/dtim.sv | 37 +++++++++++++++++++------------------
 pipelined/src/lsu/lsu.sv  |  2 +-
 3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index b2eb0039..6adc5ad2 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -177,7 +177,7 @@ module ifu (
     dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
               .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
               .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
-              .BusCommittedM(), .DCacheStallM(ICacheStallF), 
+              .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
               .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
     
   end 
diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv
index 38a12c75..6ca5be4a 100644
--- a/pipelined/src/lsu/dtim.sv
+++ b/pipelined/src/lsu/dtim.sv
@@ -30,28 +30,29 @@
 `include "wally-config.vh"
 
 module dtim(
-  input logic                 clk, reset,
-  input logic                 CPUBusy,
-  input logic [1:0]           LSURWM,
-  input logic [`XLEN-1:0]     IEUAdrM,
-  input logic [`XLEN-1:0]     IEUAdrE,
-  input logic                 TrapM, 
-  input logic [`XLEN-1:0]     FinalWriteDataM,
-  input logic [`XLEN/8-1:0]   ByteMaskM,
-  output logic [`XLEN-1:0]    ReadDataWordM,
-  output logic                BusStall,
-  output logic                LSUBusWrite,
-  output logic                LSUBusRead,
-  output logic                BusCommittedM,
-  output logic                DCacheStallM,
-  output logic                DCacheCommittedM,
-  output logic                DCacheMiss,
-  output logic                DCacheAccess);
+  input logic               clk, reset,
+  input logic               CPUBusy,
+  input logic [1:0]         LSURWM,
+  input logic [`XLEN-1:0]   IEUAdrM,
+  input logic [`XLEN-1:0]   IEUAdrE,
+  input logic               TrapM, 
+  input logic [`XLEN-1:0]   FinalWriteDataM,
+  input logic [`XLEN/8-1:0] ByteMaskM,
+  input logic               Cacheable,
+  output logic [`XLEN-1:0]  ReadDataWordM,
+  output logic              BusStall,
+  output logic              LSUBusWrite,
+  output logic              LSUBusRead,
+  output logic              BusCommittedM,
+  output logic              DCacheStallM,
+  output logic              DCacheCommittedM,
+  output logic              DCacheMiss,
+  output logic              DCacheAccess);
 
   simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
       .clk, .ByteMask(ByteMaskM),
       .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
-      .we(LSURWM[0] & ~TrapM),  // have to ignore write if Trap.
+      .we(LSURWM[0] & Cacheable & ~TrapM),  // have to ignore write if Trap.
       .wd(FinalWriteDataM), .rd(ReadDataWordM));
 
   // since we have a local memory the bus connections are all disabled.
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 2e20b3a2..aa617db6 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -192,7 +192,7 @@ module lsu (
     // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
     dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
               .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
-              .DCacheStallM, .DCacheCommittedM, .ByteMaskM,
+              .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM),
               .DCacheMiss, .DCacheAccess);
   end 
   if (`DBUS) begin : bus