forked from Github_Repos/cvw
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
eb9e1843fc
@ -131,6 +131,7 @@ module ahblite (
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else NextBusState = IDLE; // if (InstrReadF still high)
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INSTRREADC: if (~HREADY) NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
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else NextBusState = IDLE;
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default: NextBusState = IDLE;
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endcase
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// stall signals
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@ -74,14 +74,13 @@ module ifu (
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logic CompressedF;
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logic [31:0] InstrRawD, InstrE, InstrW;
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logic [31:0] nop = 32'h00000013; // instruction for NOP
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logic [`XLEN-1:0] ITLBInstrPAdrF, ICacheInstrPAdrF;
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// *** send this to the trap unit
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logic ITLBPageFaultF;
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tlb #(3) itlb(.TLBAccess(1'b1), .VirtualAddress(PCF),
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.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
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.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
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.PhysicalAddress(ITLBInstrPAdrF), .TLBMiss(ITLBMissF),
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.PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
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.TLBHit(ITLBHitF), .TLBPageFault(ITLBPageFaultF),
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.*);
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@ -97,15 +96,11 @@ module ifu (
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// assign InstrReadF = 1; // *** & ICacheMissF; add later
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// jarred 2021-03-14 Add instrution cache block to remove rd2
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assign PCPF = PCF; // Temporary workaround until iTLB is live
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icache ic(
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.*,
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.InstrPAdrF(ICacheInstrPAdrF),
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.UpperPCPF(PCPF[`XLEN-1:12]),
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.LowerPCF(PCF[11:0])
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);
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// Prioritize the iTLB for reads if it wants one
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mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
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assign PrivilegedChangePCM = RetM | TrapM;
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@ -30,34 +30,37 @@
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// Teo Ene 04/15:
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// Temporarily removed paramterized priority encoder for non-parameterized one
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// To get synthesis working quickly
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// *** We should look for a better parameterized priority encoder. This has a
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// bad code smell and might not synthesize
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//module priority_encoder #(parameter BINARY_BITS = 3) (
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// input [(2**BINARY_BITS)-1:0] one_hot,
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// output [BINARY_BITS-1:0] binary
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//);
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//
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// localparam ONE_HOT_BITS = 2**BINARY_BITS;
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//
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// genvar i, j;
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// generate
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// for (i = 0; i < ONE_HOT_BITS; i++) begin
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// for (j = 0; j < BINARY_BITS; j++) begin
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// if (i[j]) begin
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// assign binary[j] = one_hot[i];
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// end
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// end
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// end
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// endgenerate
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//
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//endmodule
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module priority_encoder #(parameter BINARY_BITS = 3) (
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input logic [7:0] one_hot,
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output logic [2:0] binary
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);
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// localparam ONE_HOT_BITS = 2**BINARY_BITS;
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/*
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genvar i, j;
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generate
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for (i = 0; i < ONE_HOT_BITS; i++) begin
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for (j = 0; j < BINARY_BITS; j++) begin
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if (i[j]) begin
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assign binary[j] = one_hot[i];
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end
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end
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end
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endgenerate
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*/
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/*
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logic [BINARY_BITS-1:0] binary_comb;
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always_comb begin
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binary_comb = 0;
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for (int i = 0; i < ONE_HOT_BITS; i++)
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if (one_hot[i]) binary_comb = i;
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end
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assign binary = binary_comb;
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*/
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always_comb
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case (one_hot)
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8'h1: binary=3'h0;
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