From ff9f1e5e72b1911ba2d93d955c70c964f2314675 Mon Sep 17 00:00:00 2001
From: Thomas Fleming <tfleming@hmc.edu>
Date: Thu, 15 Apr 2021 14:48:39 -0400
Subject: [PATCH 1/4] Connect tlb and icache properly

---
 wally-pipelined/src/ifu/ifu.sv | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index bc044300..d5ecf470 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -74,14 +74,13 @@ module ifu (
   logic             CompressedF;
   logic [31:0]      InstrRawD, InstrE, InstrW;
   logic [31:0]      nop = 32'h00000013; // instruction for NOP
-  logic [`XLEN-1:0] ITLBInstrPAdrF, ICacheInstrPAdrF;
   // *** send this to the trap unit
   logic             ITLBPageFaultF;
 
   tlb #(3) itlb(.TLBAccess(1'b1), .VirtualAddress(PCF),
                 .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
                 .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
-                .PhysicalAddress(ITLBInstrPAdrF), .TLBMiss(ITLBMissF),
+                .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
                 .TLBHit(ITLBHitF), .TLBPageFault(ITLBPageFaultF),
                 .*);
 
@@ -97,15 +96,11 @@ module ifu (
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
   // jarred 2021-03-14 Add instrution cache block to remove rd2
-  assign PCPF = PCF; // Temporary workaround until iTLB is live
   icache ic(
     .*,
-    .InstrPAdrF(ICacheInstrPAdrF),
     .UpperPCPF(PCPF[`XLEN-1:12]),
     .LowerPCF(PCF[11:0])
   );
-  // Prioritize the iTLB for reads if it wants one
-  mux2 #(`XLEN) instrPAdrMux(ICacheInstrPAdrF, ITLBInstrPAdrF, ITLBMissF, InstrPAdrF);
 
   assign PrivilegedChangePCM = RetM | TrapM;
 

From 6dd7591cebd8016a9968c350b1004f8b98f461c6 Mon Sep 17 00:00:00 2001
From: Thomas Fleming <tfleming@hmc.edu>
Date: Thu, 15 Apr 2021 16:17:35 -0400
Subject: [PATCH 3/4] Change priority encoder to avoid extra assignment

---
 wally-pipelined/src/mmu/priority_encoder.sv | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/wally-pipelined/src/mmu/priority_encoder.sv b/wally-pipelined/src/mmu/priority_encoder.sv
index 6bb22826..516fe8e3 100644
--- a/wally-pipelined/src/mmu/priority_encoder.sv
+++ b/wally-pipelined/src/mmu/priority_encoder.sv
@@ -36,6 +36,7 @@ module priority_encoder #(parameter BINARY_BITS = 3) (
 
   localparam ONE_HOT_BITS = 2**BINARY_BITS;
 
+  /*
   genvar i, j;
   generate
     for (i = 0; i < ONE_HOT_BITS; i++) begin
@@ -46,5 +47,16 @@ module priority_encoder #(parameter BINARY_BITS = 3) (
       end
     end
   endgenerate
+  */
+
+  logic [BINARY_BITS-1:0] binary_comb;
+
+  always_comb begin
+    binary_comb = 0;
+    for (int i = 0; i < ONE_HOT_BITS; i++)
+      if (one_hot[i]) binary_comb = i;
+  end
+
+  assign binary = binary_comb;
 
 endmodule

From 374a93dae6c68377316b60e356203c83489521d4 Mon Sep 17 00:00:00 2001
From: Teo Ene <teodor@rivendell.ecen.okstate.edu>
Date: Thu, 15 Apr 2021 15:29:04 -0500
Subject: [PATCH 4/4] Quick fix to ahblite missing default statement done in
 class :)

---
 wally-pipelined/src/ebu/ahblite.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index d3cd9834..919b882f 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -131,6 +131,7 @@ module ahblite (
             else                   NextBusState = IDLE;  // if (InstrReadF still high)
       INSTRREADC: if (~HREADY)     NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
             else                   NextBusState = IDLE;
+      default:                     NextBusState = IDLE;
     endcase
 
   // stall signals