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Remove busy-mmu and fix missing signal

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Thomas Fleming 2021-05-14 07:14:20 -04:00
parent e27bc1cbf7
commit ea4e76938e
2 changed files with 1 additions and 5204 deletions
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5203
wally-pipelined/regression/busy-mmu.do
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wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -120,7 +120,7 @@ module wallypipelinedhart (
logic ICacheStallF; logic ICacheStallF;
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE; logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
logic MMUStall; logic MMUStall;
logic MMUTranslate, MMUTranslationComplete, MMUReady; logic MMUTranslate, MMUReady;
// bus interface to dmem // bus interface to dmem
logic MemReadM, MemWriteM; logic MemReadM, MemWriteM;