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update to allow running of ImperasDV with linux boot

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optimize performance of the tracer
This commit is contained in:
eroom1966 2023-03-27 09:46:16 +01:00
parent 39ac6be103
commit e65cbc6636
4 changed files with 4 additions and 9 deletions
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2
config/buildroot/wally-config.vh
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@ -29,7 +29,7 @@
`include "wally-shared.vh" `include "wally-shared.vh"
`define FPGA 1 `define FPGA 1
`define QEMU 1 `define QEMU 0
// RV32 or RV64: XLEN = 32 or 64 // RV32 or RV64: XLEN = 32 or 64
`define XLEN 64 `define XLEN 64

6
sim/imperas.ic
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@ -1,4 +1,4 @@
#--mpdconsole refRoot #--mpdconsole
#--gdbconsole #--gdbconsole
--showoverrides --showoverrides
--showcommands --showcommands
@ -18,8 +18,6 @@
# illegal pmp read contained this # illegal pmp read contained this
# --override cpu/tval_ii_code=F # --override cpu/tval_ii_code=F
--registerset cpu/SCOUNTEREN=0x1
# PMA Settings # PMA Settings
# 'r': read access allowed # 'r': read access allowed
# 'w': write access allowed # 'w': write access allowed
@ -51,7 +49,7 @@
# Add Imperas simulator application instruction tracing # Add Imperas simulator application instruction tracing
--override cpu/show_c_prefix=T --override cpu/show_c_prefix=T
--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
# Exceptions and pagetables debug # Exceptions and pagetables debug
--override cpu/debugflags=6 --override cpu/debugflags=6

2
sim/run-imperas-linux.sh
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@ -4,6 +4,6 @@ export RISCV=/scratch/moore/RISCV
export IMPERAS_TOOLS=$(pwd)/imperas.ic export IMPERAS_TOOLS=$(pwd)/imperas.ic
export OTHERFLAGS="+TRACE2LOG_ENABLE=1" export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"

3
testbench/testbench-linux-imperas.sv
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@ -336,9 +336,6 @@ module testbench;
void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx
end end
// ERROR Temporary as it powers up as 0x1
void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason
// cannot predict this register due to latency between // cannot predict this register due to latency between
// pending and taken // pending and taken
void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP