From e65cbc6636c1ea7dcc7e9bbbba09f1c414273574 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 27 Mar 2023 09:46:16 +0100 Subject: [PATCH] update to allow running of ImperasDV with linux boot optimize performance of the tracer --- config/buildroot/wally-config.vh | 2 +- sim/imperas.ic | 6 ++---- sim/run-imperas-linux.sh | 2 +- testbench/testbench-linux-imperas.sv | 3 --- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index 3a68571d..23657428 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -29,7 +29,7 @@ `include "wally-shared.vh" `define FPGA 1 -`define QEMU 1 +`define QEMU 0 // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 diff --git a/sim/imperas.ic b/sim/imperas.ic index 82aedf1c..167c0cc4 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,4 +1,4 @@ -#--mpdconsole refRoot +#--mpdconsole #--gdbconsole --showoverrides --showcommands @@ -18,8 +18,6 @@ # illegal pmp read contained this # --override cpu/tval_ii_code=F ---registerset cpu/SCOUNTEREN=0x1 - # PMA Settings # 'r': read access allowed # 'w': write access allowed @@ -51,7 +49,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10000000 +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 5a21b0eb..09face55 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -4,6 +4,6 @@ export RISCV=/scratch/moore/RISCV export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" -export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10000000" +export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv index 64f745e4..20104208 100644 --- a/testbench/testbench-linux-imperas.sv +++ b/testbench/testbench-linux-imperas.sv @@ -336,9 +336,6 @@ module testbench; void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx end - // ERROR Temporary as it powers up as 0x1 - void'(rvviRefCsrSet(0, 32'h106, 1)); // RTL sets SCOUNTEREN to 1 for some reason - // cannot predict this register due to latency between // pending and taken void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP