From e5955c5dd8d36cf98a6ea7345699e691fced6621 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 28 Mar 2023 10:28:01 -0700 Subject: [PATCH] support more fp -> fp conversions --- src/fpu/fctrl.sv | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 8428b8c7..5e7dd1ae 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -150,10 +150,14 @@ module fctrl ( ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg - 7'b0100000: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d - 7'b0100001: if (Rs2D[4:2] == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s + 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) + 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) + 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) + ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.h.(s/d//h) + 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) + ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.q.(s/h/d) // *** other formats here /* verilator lint_off CASEINCOMPLETE */ 7'b1101000: case(Rs2D)