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Rename of DCacheMem to cacheway.

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simplified dcache names.
This commit is contained in:
Ross Thompson 2021-08-25 13:33:15 -05:00
parent e9a1dc90f6
commit e5336f4ee1
2 changed files with 9 additions and 10 deletions
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2
wally-pipelined/src/cache/DCacheMem.sv → wally-pipelined/src/cache/cacheway.sv vendored
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@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
parameter OFFSETLEN, parameter INDEXLEN) parameter OFFSETLEN, parameter INDEXLEN)
(input logic clk, (input logic clk,
input logic reset, input logic reset,

17
wally-pipelined/src/cache/dcache.sv vendored
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@ -202,10 +202,9 @@ module dcache
assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW;
DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) MemWay[NUMWAYS-1:0](.clk,
MemWay[NUMWAYS-1:0](.clk(clk), .reset,
.reset(reset),
.Adr(SRAMAdr), .Adr(SRAMAdr),
.MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
@ -218,11 +217,11 @@ module dcache
.SetDirty(SetDirtyM), .SetDirty(SetDirtyM),
.ClearDirty(ClearDirtyM), .ClearDirty(ClearDirtyM),
.SelEvict, .SelEvict,
.VictimWay(VictimWay), .VictimWay,
.ReadDataBlockWayMaskedM(ReadDataBlockWayMaskedM), .ReadDataBlockWayMaskedM,
.WayHit(WayHit), .WayHit,
.VictimDirtyWay(VictimDirtyWay), .VictimDirtyWay,
.VictimTagWay(VictimTagWay)); .VictimTagWay);
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) begin if (reset) begin