forked from Github_Repos/cvw
1041 lines
28 KiB
Systemverilog
1041 lines
28 KiB
Systemverilog
///////////////////////////////////////////
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// dcache (data cache)
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the L1 data cache
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//
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// Purpose: Storage for data and meta data.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module dcache
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(input logic clk,
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input logic reset,
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input logic StallM,
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input logic StallWtoDCache,
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input logic FlushM,
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input logic FlushW,
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// cpu side
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] MemPAdrM, // physical address
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input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
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input logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] ReadDataM,
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output logic DCacheStall,
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output logic CommittedM,
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output logic DCacheMiss,
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output logic DCacheAccess,
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// inputs from TLB and PMA/P
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input logic ExceptionM,
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input logic PendingInterruptM,
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input logic DTLBMissM,
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input logic ITLBMissF,
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input logic CacheableM,
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input logic DTLBWriteM,
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input logic ITLBWriteF,
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input logic WalkerInstrPageFaultF,
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// from ptw
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input logic SelPTW,
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input logic WalkerPageFaultM,
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output logic MemAfterIWalkDone,
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// ahb side
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output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
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output logic AHBRead,
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output logic AHBWrite,
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input logic AHBAck, // from ahb
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input logic [`XLEN-1:0] HRDATA, // from ahb
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output logic [`XLEN-1:0] HWDATA // to ahb
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);
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/* localparam integer BLOCKLEN = 256;
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localparam integer NUMLINES = 64;
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localparam integer NUMWAYS = 4;
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localparam integer NUMREPL_BITS = 3;*/
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localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
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localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN;
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localparam integer NUMWAYS = `DCACHE_NUMWAYS;
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localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; // *** not used
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localparam integer BLOCKBYTELEN = BLOCKLEN/8;
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localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
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localparam integer INDEXLEN = $clog2(NUMLINES);
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localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
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localparam integer WORDSPERLINE = BLOCKLEN/`XLEN;
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localparam integer LOGWPL = $clog2(WORDSPERLINE);
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localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
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logic [1:0] SelAdrM;
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logic [INDEXLEN-1:0] SRAMAdr;
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logic [BLOCKLEN-1:0] SRAMWriteData;
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logic [BLOCKLEN-1:0] DCacheMemWriteData;
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logic SetValidM, ClearValidM;
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logic SetDirtyM, ClearDirtyM;
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logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] WayHit;
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logic CacheHit;
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logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
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logic [NUMWAYS-2:0] BlockReplacementBits;
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logic [NUMWAYS-2:0] NewReplacement;
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logic [BLOCKLEN-1:0] ReadDataBlockM;
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logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
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logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
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logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
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logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
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logic [LOGWPL-1:0] FetchCount, NextFetchCount;
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logic [WORDSPERLINE-1:0] SRAMWordEnable;
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logic SRAMWordWriteEnableM;
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logic SRAMBlockWriteEnableM;
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logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM;
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logic SRAMWriteEnable;
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logic [NUMWAYS-1:0] SRAMWayWriteEnable;
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logic [NUMWAYS-1:0] VictimWay;
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logic [NUMWAYS-1:0] VictimDirtyWay;
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logic [BLOCKLEN-1:0] VictimReadDataBlockM;
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logic VictimDirty;
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logic SelUncached;
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logic [2**LOGWPL-1:0] MemPAdrDecodedW;
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logic [`PA_BITS-1:0] BasePAdrM;
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logic [OFFSETLEN-1:0] BasePAdrOffsetM;
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logic [`PA_BITS-1:0] BasePAdrMaskedM;
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logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] VictimTag;
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logic AnyCPUReqM;
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logic FetchCountFlag;
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logic PreCntEn;
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logic CntEn;
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logic CntReset;
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logic SelEvict;
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logic LRUWriteEn;
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typedef enum {STATE_READY,
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STATE_MISS_FETCH_WDV,
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STATE_MISS_FETCH_DONE,
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STATE_MISS_EVICT_DIRTY,
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STATE_MISS_WRITE_CACHE_BLOCK,
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STATE_MISS_READ_WORD,
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STATE_MISS_READ_WORD_DELAY,
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STATE_MISS_WRITE_WORD,
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STATE_PTW_READY,
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STATE_PTW_READ_MISS_FETCH_WDV,
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STATE_PTW_READ_MISS_FETCH_DONE,
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STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_READ_MISS_EVICT_DIRTY,
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STATE_PTW_READ_MISS_READ_WORD,
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STATE_PTW_READ_MISS_READ_WORD_DELAY,
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STATE_PTW_ACCESS_AFTER_WALK,
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STATE_UNCACHED_WRITE,
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STATE_UNCACHED_WRITE_DONE,
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STATE_UNCACHED_READ,
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STATE_UNCACHED_READ_DONE,
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STATE_PTW_FAULT_READY,
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STATE_PTW_FAULT_CPU_BUSY,
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STATE_PTW_FAULT_MISS_FETCH_WDV,
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STATE_PTW_FAULT_MISS_FETCH_DONE,
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STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_FAULT_MISS_READ_WORD,
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STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
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STATE_PTW_FAULT_MISS_WRITE_WORD,
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STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
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STATE_PTW_FAULT_MISS_EVICT_DIRTY,
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STATE_PTW_FAULT_UNCACHED_WRITE,
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STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
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STATE_PTW_FAULT_UNCACHED_READ,
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STATE_PTW_FAULT_UNCACHED_READ_DONE,
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STATE_CPU_BUSY,
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STATE_CPU_BUSY_FINISH_AMO} statetype;
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statetype CurrState, NextState;
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// data path
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mux3 #(INDEXLEN)
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AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.s(SelAdrM),
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.y(SRAMAdr));
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onehotdecoder #(LOGWPL)
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adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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.decoded(MemPAdrDecodedW));
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assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW;
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cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
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MemWay[NUMWAYS-1:0](.clk,
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.reset,
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.Adr(SRAMAdr),
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.MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
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.WriteEnable(SRAMWayWriteEnable),
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.WriteWordEnable(SRAMWordEnable),
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.TagWriteEnable(SRAMBlockWayWriteEnableM),
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.WriteData(SRAMWriteData),
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.WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
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.SetValid(SetValidM),
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.ClearValid(ClearValidM),
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.SetDirty(SetDirtyM),
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.ClearDirty(ClearDirtyM),
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.SelEvict,
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.VictimWay,
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.ReadDataBlockWayMaskedM,
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.WayHit,
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.VictimDirtyWay,
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.VictimTagWay);
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always_ff @(posedge clk, posedge reset) begin
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if (reset) begin
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for(int index = 0; index < NUMLINES; index++)
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ReplacementBits[index] <= '0;
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end else begin
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BlockReplacementBits <= ReplacementBits[SRAMAdr];
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if (LRUWriteEn) begin
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ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
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end
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end
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end
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// *** TODO only supports 1, 2, 4, and 8 way
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generate
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if(NUMWAYS > 1) begin
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cacheLRU #(NUMWAYS)
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cacheLRU(.LRUIn(BlockReplacementBits),
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.WayIn(WayHit),
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.LRUOut(NewReplacement),
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.VictimWay(VictimWay));
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end else begin
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assign NewReplacement = '0;
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assign VictimWay = 1'b1;
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end
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endgenerate
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assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0;
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
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.d1(SRAMBlockWayWriteEnableM),
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.s(SRAMBlockWriteEnableM),
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.y(SRAMWayWriteEnable));
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assign CacheHit = |WayHit;
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// ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways.
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// Need to OR together each way in a bitwise manner.
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// Final part of the AO Mux.
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genvar index;
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always_comb begin
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ReadDataBlockM = '0;
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VictimReadDataBlockM = '0;
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VictimTag = '0;
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for(int index = 0; index < NUMWAYS; index++) begin
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ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index];
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VictimTag = VictimTag | VictimTagWay[index];
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end
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end
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assign VictimDirty = | VictimDirtyWay;
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// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
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// easily build a variable input mux.
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// *** consider using a limited range shift to do this final muxing.
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generate
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for (index = 0; index < WORDSPERLINE; index++) begin
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assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)];
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end
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endgenerate
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// variable input mux
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assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
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assign HWDATA = CacheableM ? ReadDataBlockSetsM[FetchCount] : WriteDataM;
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mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
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.d1(DCacheMemWriteData[`XLEN-1:0]),
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.s(SelUncached),
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.y(ReadDataWordMuxM));
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// finally swr
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// *** BUG fix HSIZED? why was it this way?
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subwordread subwordread(.HRDATA(ReadDataWordMuxM),
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.HADDRD(MemPAdrM[2:0]),
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.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
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.HRDATAMasked(ReadDataM));
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generate
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if (`A_SUPPORTED) begin
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logic [`XLEN-1:0] AMOResult;
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amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], FinalAMOWriteDataM);
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end else
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assign FinalAMOWriteDataM = WriteDataM;
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endgenerate
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// write path
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subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
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.HADDRD(MemPAdrM[2:0]),
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.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
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.HWDATAIN(FinalAMOWriteDataM),
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.HWDATA(FinalWriteDataM));
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// register the fetch data from the next level of memory.
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generate
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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flopen #(`XLEN) fb(.clk(clk),
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.en(AHBAck & AHBRead & (index == FetchCount)),
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.d(HRDATA),
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.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
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end
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endgenerate
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mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
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.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.s(SelEvict),
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.y(BasePAdrM));
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// if not cacheable the offset bits needs to be sent to the EBU.
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// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
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assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
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assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
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assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
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// mux between the CPU's write and the cache fetch.
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generate
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for(index = 0; index < WORDSPERLINE; index++) begin
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assign FinalWriteDataWordsM[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataM;
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end
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endgenerate
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mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsM),
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.d1(DCacheMemWriteData),
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.s(SRAMBlockWriteEnableM),
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.y(SRAMWriteData));
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// control path *** eventually move to own module.
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localparam FetchCountThreshold = WORDSPERLINE - 1;
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assign AnyCPUReqM = |MemRWM | (|AtomicM);
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assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
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flopenr #(LOGWPL)
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FetchCountReg(.clk(clk),
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.reset(reset | CntReset),
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.en(CntEn),
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.d(NextFetchCount),
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.q(FetchCount));
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assign NextFetchCount = FetchCount + 1'b1;
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assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
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always_ff @(posedge clk, posedge reset)
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if (reset) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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// next state logic and some state ouputs.
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always_comb begin
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DCacheStall = 1'b0;
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SelAdrM = 2'b00;
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PreCntEn = 1'b0;
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SetValidM = 1'b0;
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ClearValidM = 1'b0;
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SetDirtyM = 1'b0;
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ClearDirtyM = 1'b0;
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SRAMWordWriteEnableM = 1'b0;
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SRAMBlockWriteEnableM = 1'b0;
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CntReset = 1'b0;
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AHBRead = 1'b0;
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AHBWrite = 1'b0;
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CommittedM = 1'b0;
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SelUncached = 1'b0;
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SelEvict = 1'b0;
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DCacheAccess = 1'b0;
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DCacheMiss = 1'b0;
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LRUWriteEn = 1'b0;
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MemAfterIWalkDone = 1'b0;
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case (CurrState)
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STATE_READY: begin
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// TLB Miss
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if((AnyCPUReqM & DTLBMissM) | ITLBMissF) begin
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// the LSU arbiter has not yet selected the PTW.
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// The CPU needs to be stalled until that happens.
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// If we set DCacheStall for 1 cycle before going to
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// PTW ready the CPU will stall.
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// The page table walker asserts it's control 1 cycle
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// after the TLBs miss.
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CommittedM = 1'b1;
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DCacheStall = 1'b1;
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NextState = STATE_PTW_READY;
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end
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// amo hit
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else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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SelAdrM = 2'b01;
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DCacheStall = 1'b0;
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if(StallWtoDCache) begin
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NextState = STATE_CPU_BUSY_FINISH_AMO;
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SelAdrM = 2'b01;
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end
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else begin
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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LRUWriteEn = 1'b1;
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NextState = STATE_READY;
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end
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end
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// read hit valid cached
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else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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DCacheStall = 1'b0;
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DCacheAccess = 1'b1;
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LRUWriteEn = 1'b1;
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if(StallWtoDCache) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b01;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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// write hit valid cached
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else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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SelAdrM = 2'b01;
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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LRUWriteEn = 1'b1;
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if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
// read or write miss valid cached
|
|
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
|
|
NextState = STATE_MISS_FETCH_WDV;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
DCacheAccess = 1'b1;
|
|
DCacheMiss = 1'b1;
|
|
end
|
|
// uncached write
|
|
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
|
NextState = STATE_UNCACHED_WRITE;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
end
|
|
// uncached read
|
|
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
|
NextState = STATE_UNCACHED_READ;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
AHBRead = 1'b1;
|
|
end
|
|
// fault
|
|
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
|
NextState = STATE_READY;
|
|
end
|
|
else NextState = STATE_READY;
|
|
end
|
|
|
|
STATE_MISS_FETCH_WDV: begin
|
|
DCacheStall = 1'b1;
|
|
PreCntEn = 1'b1;
|
|
AHBRead = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
|
|
if (FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_MISS_FETCH_DONE;
|
|
end else begin
|
|
NextState = STATE_MISS_FETCH_WDV;
|
|
end
|
|
end
|
|
|
|
STATE_MISS_FETCH_DONE: begin
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CntReset = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(VictimDirty) begin
|
|
NextState = STATE_MISS_EVICT_DIRTY;
|
|
end else begin
|
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
|
end
|
|
end
|
|
|
|
STATE_MISS_WRITE_CACHE_BLOCK: begin
|
|
SRAMBlockWriteEnableM = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
NextState = STATE_MISS_READ_WORD;
|
|
SelAdrM = 2'b01;
|
|
SetValidM = 1'b1;
|
|
ClearDirtyM = 1'b1;
|
|
CommittedM = 1'b1;
|
|
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
|
end
|
|
|
|
STATE_MISS_READ_WORD: begin
|
|
SelAdrM = 2'b01;
|
|
DCacheStall = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if (MemRWM[0]) begin // handles stores and amo write.
|
|
NextState = STATE_MISS_WRITE_WORD;
|
|
end else begin
|
|
NextState = STATE_MISS_READ_WORD_DELAY;
|
|
// delay state is required as the read signal MemRWM[1] is still high when we
|
|
// return to the ready state because the cache is stalling the cpu.
|
|
end
|
|
end
|
|
|
|
STATE_MISS_READ_WORD_DELAY: begin
|
|
//SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
if(&MemRWM & AtomicM[1]) begin // amo write
|
|
SelAdrM = 2'b01;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
|
end
|
|
else begin
|
|
SRAMWordWriteEnableM = 1'b1;
|
|
SetDirtyM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end else begin
|
|
LRUWriteEn = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
end
|
|
|
|
STATE_MISS_WRITE_WORD: begin
|
|
SRAMWordWriteEnableM = 1'b1;
|
|
SetDirtyM = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_MISS_EVICT_DIRTY: begin
|
|
DCacheStall = 1'b1;
|
|
PreCntEn = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
SelEvict = 1'b1;
|
|
if( FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
|
end else begin
|
|
NextState = STATE_MISS_EVICT_DIRTY;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_READY: begin
|
|
// now all output connect to PTW instead of CPU.
|
|
CommittedM = 1'b1;
|
|
|
|
// In this branch we remove stall and go back to ready. There is no request for memory from the
|
|
// datapath or the walker had a fault.
|
|
// types 3b, 4a, 4b, and 7c.
|
|
if ((DTLBMissM & WalkerPageFaultM) | // 3b
|
|
(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
|
|
(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c
|
|
NextState = STATE_READY;
|
|
DCacheStall = 1'b0;
|
|
end
|
|
// in this branch we go back to ready, but there is a memory operation from
|
|
// the datapath so we MUST stall and replay the operation.
|
|
// types 3a and 5a
|
|
else if ((DTLBMissM & DTLBWriteM) | // 3a
|
|
(ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
|
|
NextState = STATE_READY;
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b10;
|
|
end
|
|
|
|
// like 5a we want to stall and go to the ready state, but we also have to save
|
|
// the WalkerInstrPageFaultF so it is held until the end of the memory operation
|
|
// from the datapath.
|
|
// types 5b
|
|
else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
|
|
NextState = STATE_PTW_FAULT_READY;
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b10;
|
|
end
|
|
|
|
// in this branch we stay in ptw_ready because we are doing an itlb walk
|
|
// after a dtlb walk.
|
|
// types 7a and 7b.
|
|
else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
|
|
NextState = STATE_PTW_READY;
|
|
DCacheStall = 1'b0;
|
|
|
|
// read hit valid cached
|
|
end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
|
|
NextState = STATE_PTW_READY;
|
|
DCacheStall = 1'b0;
|
|
LRUWriteEn = 1'b1;
|
|
end
|
|
|
|
// read miss valid cached
|
|
else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
|
|
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
end
|
|
|
|
else begin
|
|
NextState = STATE_PTW_READY;
|
|
DCacheStall = 1'b0;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
|
DCacheStall = 1'b1;
|
|
PreCntEn = 1'b1;
|
|
AHBRead = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
|
|
if (FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_PTW_READ_MISS_FETCH_DONE;
|
|
end else begin
|
|
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_READ_MISS_FETCH_DONE: begin
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CntReset = 1'b1;
|
|
CommittedM = 1'b1;
|
|
CntReset = 1'b1;
|
|
if(VictimDirty) begin
|
|
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
|
end else begin
|
|
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_READ_MISS_EVICT_DIRTY: begin
|
|
DCacheStall = 1'b1;
|
|
PreCntEn = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
SelEvict = 1'b1;
|
|
if(FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
|
end else begin
|
|
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
|
end
|
|
end
|
|
|
|
|
|
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
|
|
SRAMBlockWriteEnableM = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
NextState = STATE_PTW_READ_MISS_READ_WORD;
|
|
SelAdrM = 2'b01;
|
|
SetValidM = 1'b1;
|
|
ClearDirtyM = 1'b1;
|
|
CommittedM = 1'b1;
|
|
//LRUWriteEn = 1'b1;
|
|
end
|
|
|
|
STATE_PTW_READ_MISS_READ_WORD: begin
|
|
SelAdrM = 2'b01;
|
|
DCacheStall = 1'b1;
|
|
CommittedM = 1'b1;
|
|
NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
|
|
end
|
|
|
|
STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
|
|
SelAdrM = 2'b01;
|
|
NextState = STATE_PTW_READY;
|
|
CommittedM = 1'b1;
|
|
end
|
|
|
|
STATE_PTW_ACCESS_AFTER_WALK: begin
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
|
|
STATE_CPU_BUSY: begin
|
|
CommittedM = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_CPU_BUSY_FINISH_AMO: begin
|
|
CommittedM = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
|
end
|
|
else begin
|
|
SRAMWordWriteEnableM = 1'b1;
|
|
SetDirtyM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_UNCACHED_WRITE : begin
|
|
DCacheStall = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(AHBAck) begin
|
|
NextState = STATE_UNCACHED_WRITE_DONE;
|
|
end else begin
|
|
NextState = STATE_UNCACHED_WRITE;
|
|
end
|
|
end
|
|
|
|
STATE_UNCACHED_READ : begin
|
|
DCacheStall = 1'b1;
|
|
AHBRead = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(AHBAck) begin
|
|
NextState = STATE_UNCACHED_READ_DONE;
|
|
end else begin
|
|
NextState = STATE_UNCACHED_READ;
|
|
end
|
|
end
|
|
|
|
STATE_UNCACHED_WRITE_DONE: begin
|
|
CommittedM = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_UNCACHED_READ_DONE: begin
|
|
CommittedM = 1'b1;
|
|
SelUncached = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
|
|
// itlb => instruction page fault states with memory request.
|
|
STATE_PTW_FAULT_READY: begin
|
|
// read hit valid cached
|
|
if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
|
|
DCacheStall = 1'b0;
|
|
DCacheAccess = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
// write hit valid cached
|
|
else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
|
|
SelAdrM = 2'b01;
|
|
DCacheStall = 1'b0;
|
|
SRAMWordWriteEnableM = 1'b1;
|
|
SetDirtyM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
// read or write miss valid cached
|
|
else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
|
|
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
DCacheAccess = 1'b1;
|
|
DCacheMiss = 1'b1;
|
|
end
|
|
// uncached write
|
|
else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
end
|
|
// uncached read
|
|
else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
|
CntReset = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
AHBRead = 1'b1;
|
|
end
|
|
// fault
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_CPU_BUSY: begin
|
|
CommittedM = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_FETCH_WDV: begin
|
|
DCacheStall = 1'b1;
|
|
PreCntEn = 1'b1;
|
|
AHBRead = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
|
|
if (FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_FETCH_DONE: begin
|
|
DCacheStall = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
CntReset = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(VictimDirty) begin
|
|
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
|
|
SRAMBlockWriteEnableM = 1'b1;
|
|
DCacheStall = 1'b1;
|
|
NextState = STATE_PTW_FAULT_MISS_READ_WORD;
|
|
SelAdrM = 2'b01;
|
|
SetValidM = 1'b1;
|
|
ClearDirtyM = 1'b1;
|
|
CommittedM = 1'b1;
|
|
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_READ_WORD: begin
|
|
SelAdrM = 2'b01;
|
|
DCacheStall = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if (MemRWM[1]) begin
|
|
NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
|
|
// delay state is required as the read signal MemRWM[1] is still high when we
|
|
// return to the ready state because the cache is stalling the cpu.
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
|
|
CommittedM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_WRITE_WORD: begin
|
|
SRAMWordWriteEnableM = 1'b1;
|
|
SetDirtyM = 1'b1;
|
|
SelAdrM = 2'b01;
|
|
DCacheStall = 1'b1;
|
|
CommittedM = 1'b1;
|
|
LRUWriteEn = 1'b1;
|
|
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
|
|
end
|
|
|
|
STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
|
|
CommittedM = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
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|
|
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STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
|
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DCacheStall = 1'b1;
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PreCntEn = 1'b1;
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AHBWrite = 1'b1;
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SelAdrM = 2'b01;
|
|
CommittedM = 1'b1;
|
|
SelEvict = 1'b1;
|
|
if(FetchCountFlag & AHBAck) begin
|
|
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
|
end
|
|
end
|
|
|
|
|
|
STATE_PTW_FAULT_UNCACHED_WRITE : begin
|
|
DCacheStall = 1'b1;
|
|
AHBWrite = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(AHBAck) begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_UNCACHED_READ : begin
|
|
DCacheStall = 1'b1;
|
|
AHBRead = 1'b1;
|
|
CommittedM = 1'b1;
|
|
if(AHBAck) begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
|
|
end else begin
|
|
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
|
|
CommittedM = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
|
|
CommittedM = 1'b1;
|
|
SelUncached = 1'b1;
|
|
if(StallWtoDCache) begin
|
|
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
|
SelAdrM = 2'b01;
|
|
end
|
|
else begin
|
|
MemAfterIWalkDone = 1'b1;
|
|
NextState = STATE_READY;
|
|
end
|
|
end
|
|
|
|
default: begin
|
|
end
|
|
endcase
|
|
end
|
|
|
|
assign CntEn = PreCntEn & AHBAck;
|
|
|
|
endmodule // dcache
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