some cleanup of signals, not done yet

wally-pipelined/src/dmem/dmem.sv

@@ -96,7 +96,7 @@ module dmem (
   // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
   
   mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
-                .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM),
+                .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
                 .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
                 .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
                 .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),

wally-pipelined/src/ifu/ifu.sv

@@ -107,7 +107,7 @@ module ifu (
   // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
 
   mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
-                .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
+                .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF),
                 .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
                 .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
                 .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),

wally-pipelined/src/mmu/cam_line.sv

@@ -32,15 +32,15 @@ module cam_line #(parameter KEY_BITS = 20,
                   parameter HIGH_SEGMENT_BITS = 10) (
   input                 clk, reset,
 
-  // input to scheck which SvMode is running
+  // input to check which SvMode is running
-  input [`SVMODE_BITS-1:0] SvMode,
+//  input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
   
   // The requested page number to compare against the key
   input [KEY_BITS-1:0]  VirtualPageNumber,
 
   // Signals to write a new entry to this line
-  input                 CAMLineWrite,
+  input logic                 CAMLineWrite,
-  input  [1:0]          PageTypeWrite,
+  input logic [1:0]           PageTypeWriteVal,
 
   // Flush this line (set valid to 0)
   input                 TLBFlush,
@@ -58,13 +58,8 @@ module cam_line #(parameter KEY_BITS = 20,
   logic                Valid;
   logic [KEY_BITS-1:0] Key;
 
-  // When determining a match for a superpage, we might use only a portion of
-  // the input VirtualPageNumber. Unused parts of the VirtualPageNumber are
-  // zeroed in VirtualPageNumberQuery to better match with Key.
-  logic [KEY_BITS-1:0] VirtualPageNumberQuery;
-
   // On a write, update the type of the page referred to by this line.
-  flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWrite, PageType);
+  flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType);
   //mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType);
 
   // On a write, set the valid bit high and update the stored key.

wally-pipelined/src/mmu/mmu.sv

@@ -49,8 +49,8 @@ module mmu #(parameter ENTRY_BITS = 3,
   input logic  [`XLEN-1:0] VirtualAddress,
 
   // Controls for writing a new entry to the TLB
-  input logic  [`XLEN-1:0] PageTableEntryWrite,
+  input logic  [`XLEN-1:0] PTEWriteVal,
-  input logic  [1:0]       PageTypeWrite,
+  input logic  [1:0]       PageTypeWriteVal,
   input logic              TLBWrite,
 
   // Invalidate all TLB entries

wally-pipelined/src/mmu/pmachecker.sv

@@ -28,13 +28,13 @@
 `include "wally-config.vh"
 
 module pmachecker (
-  input  logic        clk, reset,
+//  input  logic        clk, reset, // *** unused in this module and all sub modules.
 
   input  logic [31:0] HADDR,
   input  logic [2:0]  HSIZE,
-  input  logic [2:0]  HBURST,
+//  input  logic [2:0]  HBURST, //  *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.
 
-  input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
+  input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
 
   output logic        Cacheable, Idempotent, AtomicAllowed,
   output logic        PMASquashBusAccess,
@@ -92,7 +92,7 @@ module pmachecker (
 endmodule
 
 module attributes (
-  input  logic        clk, reset,
+//  input  logic        clk, reset, // *** unused in this module and all sub modules.
 
   input  logic [31:0] Address,
 

wally-pipelined/src/mmu/pmpchecker.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module pmpchecker (
-  input  logic             clk, reset,
+//  input  logic             clk, reset, //*** it seems like clk, reset is also not needed here?
 
   input  logic [31:0]      HADDR,
 

wally-pipelined/src/mmu/tlb.sv

@@ -71,8 +71,8 @@ module tlb #(parameter ENTRY_BITS = 3,
   input logic  [`XLEN-1:0] VirtualAddress,
 
   // Controls for writing a new entry to the TLB
-  input logic  [`XLEN-1:0] PageTableEntryWrite,
+  input logic  [`XLEN-1:0] PTEWriteVal,
-  input logic  [1:0]       PageTypeWrite,
+  input logic  [1:0]       PageTypeWriteVal,
   input logic              TLBWrite,
 
   // Invalidate all TLB entries

wally-pipelined/src/mmu/tlb_cam.sv

@@ -30,17 +30,18 @@
 
 module tlb_cam #(parameter ENTRY_BITS = 3,
                  parameter KEY_BITS   = 20,
-                 parameter HIGH_SEGMENT_BITS = 10) (
+                 parameter SEGMENT_BITS = 10) (
-  input                     clk, reset,
+  input logic                     clk, reset,
-  input  [KEY_BITS-1:0]     VirtualPageNumber,
+  input logic [KEY_BITS-1:0]      VirtualPageNumber,
-  input  [1:0]              PageTypeWrite,
+  input logic [1:0]               PageTypeWriteVal,
-  input  [ENTRY_BITS-1:0]   WriteIndex,
+//  input logic [`SVMODE_BITS-1:0]  SvMode, // *** may not need to be used.
-  input  [`SVMODE_BITS-1:0] SvMode,
+  input logic                     TLBWrite,
-  input                     TLBWrite,
+  input logic                     TLBFlush,
-  input                     TLBFlush,
+  input logic [2**ENTRY_BITS-1:0] WriteLines,
-  output [ENTRY_BITS-1:0]   VPNIndex,
+
-  output [1:0]              HitPageType,
+  output logic [ENTRY_BITS-1:0]   VPNIndex,
-  output                    CAMHit
+  output logic [1:0]              HitPageType,
+  output logic                    CAMHit
 );
 
   localparam NENTRIES = 2**ENTRY_BITS;
@@ -71,7 +72,7 @@ module tlb_cam #(parameter ENTRY_BITS = 3,
   // In case there are multiple matches in the CAM, select only one
   // *** it might be guaranteed that the CAM will never have multiple matches.
   // If so, this is just an encoder
-  priority_encoder #(ENTRY_BITS) match_priority(Matches, VPNIndex);
+  priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
 
   assign CAMHit = |Matches & ~TLBFlush;
   assign HitPageType = PageTypeList[VPNIndex];

wally-pipelined/src/mmu/tlb_ram.sv

@@ -28,12 +28,13 @@
 `include "wally-config.vh"
 `include "wally-constants.vh"
 
-module tlb_ram #(parameter ENTRY_BITS = 3) (
+module tlbram #(parameter ENTRY_BITS = 3) (
-  input                   clk, reset,
+  input logic                       clk, reset,
-  input  [ENTRY_BITS-1:0] VPNIndex,  // Index to read from
+  input logic [ENTRY_BITS-1:0]      VPNIndex,  // Index to read from
-  input  [ENTRY_BITS-1:0] WriteIndex,
+//  input logic [ENTRY_BITS-1:0]      WriteIndex, // *** unused?
-  input  [`XLEN-1:0]      PageTableEntryWrite,
+  input logic [`XLEN-1:0]           PTEWriteVal,
-  input                   TLBWrite,
+  input logic                       TLBWrite,
+  input logic [2**ENTRY_BITS-1:0]   WriteLines,
 
   output [`PPN_BITS-1:0]  PhysicalPageNumber,
   output [7:0]            PTEAccessBits
@@ -51,9 +52,9 @@ module tlb_ram #(parameter ENTRY_BITS = 3) (
   // Generate a flop for every entry in the RAM
   generate
     genvar i;
-    for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops
+    for (i = 0; i < NENTRIES; i++) begin:  tlb_ram_flops
-      flopenr #(`XLEN) pte_flop(clk, reset, RAMEntryWrite[i] & TLBWrite,
+      flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite,
-        PageTableEntryWrite, ram[i]);
+        PTEWriteVal, ram[i]);
     end
   endgenerate