diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index deaef9a9..229cf52c 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -96,7 +96,7 @@ module dmem ( // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), - .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM), + .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 8df871f3..a9ff48e5 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -107,7 +107,7 @@ module ifu ( // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), - .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), + .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/cam_line.sv index 6bab0b60..297f3fa8 100644 --- a/wally-pipelined/src/mmu/cam_line.sv +++ b/wally-pipelined/src/mmu/cam_line.sv @@ -32,15 +32,15 @@ module cam_line #(parameter KEY_BITS = 20, parameter HIGH_SEGMENT_BITS = 10) ( input clk, reset, - // input to scheck which SvMode is running - input [`SVMODE_BITS-1:0] SvMode, + // input to check which SvMode is running +// input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed. // The requested page number to compare against the key input [KEY_BITS-1:0] VirtualPageNumber, // Signals to write a new entry to this line - input CAMLineWrite, - input [1:0] PageTypeWrite, + input logic CAMLineWrite, + input logic [1:0] PageTypeWriteVal, // Flush this line (set valid to 0) input TLBFlush, @@ -58,13 +58,8 @@ module cam_line #(parameter KEY_BITS = 20, logic Valid; logic [KEY_BITS-1:0] Key; - // When determining a match for a superpage, we might use only a portion of - // the input VirtualPageNumber. Unused parts of the VirtualPageNumber are - // zeroed in VirtualPageNumberQuery to better match with Key. - logic [KEY_BITS-1:0] VirtualPageNumberQuery; - // On a write, update the type of the page referred to by this line. - flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWrite, PageType); + flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType); //mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType); // On a write, set the valid bit high and update the stored key. diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv index 58935eb9..94dbfc8d 100644 --- a/wally-pipelined/src/mmu/mmu.sv +++ b/wally-pipelined/src/mmu/mmu.sv @@ -49,8 +49,8 @@ module mmu #(parameter ENTRY_BITS = 3, input logic [`XLEN-1:0] VirtualAddress, // Controls for writing a new entry to the TLB - input logic [`XLEN-1:0] PageTableEntryWrite, - input logic [1:0] PageTypeWrite, + input logic [`XLEN-1:0] PTEWriteVal, + input logic [1:0] PageTypeWriteVal, input logic TLBWrite, // Invalidate all TLB entries diff --git a/wally-pipelined/src/mmu/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv index db4c648b..61c02426 100644 --- a/wally-pipelined/src/mmu/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -28,13 +28,13 @@ `include "wally-config.vh" module pmachecker ( - input logic clk, reset, +// input logic clk, reset, // *** unused in this module and all sub modules. input logic [31:0] HADDR, input logic [2:0] HSIZE, - input logic [2:0] HBURST, +// input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused. - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use. output logic Cacheable, Idempotent, AtomicAllowed, output logic PMASquashBusAccess, @@ -92,7 +92,7 @@ module pmachecker ( endmodule module attributes ( - input logic clk, reset, +// input logic clk, reset, // *** unused in this module and all sub modules. input logic [31:0] Address, diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 261475a4..d409b14f 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module pmpchecker ( - input logic clk, reset, +// input logic clk, reset, //*** it seems like clk, reset is also not needed here? input logic [31:0] HADDR, diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 7a6740d1..e0e51542 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -71,8 +71,8 @@ module tlb #(parameter ENTRY_BITS = 3, input logic [`XLEN-1:0] VirtualAddress, // Controls for writing a new entry to the TLB - input logic [`XLEN-1:0] PageTableEntryWrite, - input logic [1:0] PageTypeWrite, + input logic [`XLEN-1:0] PTEWriteVal, + input logic [1:0] PageTypeWriteVal, input logic TLBWrite, // Invalidate all TLB entries diff --git a/wally-pipelined/src/mmu/tlb_cam.sv b/wally-pipelined/src/mmu/tlb_cam.sv index 78d9ff8d..0a0ec145 100644 --- a/wally-pipelined/src/mmu/tlb_cam.sv +++ b/wally-pipelined/src/mmu/tlb_cam.sv @@ -30,17 +30,18 @@ module tlb_cam #(parameter ENTRY_BITS = 3, parameter KEY_BITS = 20, - parameter HIGH_SEGMENT_BITS = 10) ( - input clk, reset, - input [KEY_BITS-1:0] VirtualPageNumber, - input [1:0] PageTypeWrite, - input [ENTRY_BITS-1:0] WriteIndex, - input [`SVMODE_BITS-1:0] SvMode, - input TLBWrite, - input TLBFlush, - output [ENTRY_BITS-1:0] VPNIndex, - output [1:0] HitPageType, - output CAMHit + parameter SEGMENT_BITS = 10) ( + input logic clk, reset, + input logic [KEY_BITS-1:0] VirtualPageNumber, + input logic [1:0] PageTypeWriteVal, +// input logic [`SVMODE_BITS-1:0] SvMode, // *** may not need to be used. + input logic TLBWrite, + input logic TLBFlush, + input logic [2**ENTRY_BITS-1:0] WriteLines, + + output logic [ENTRY_BITS-1:0] VPNIndex, + output logic [1:0] HitPageType, + output logic CAMHit ); localparam NENTRIES = 2**ENTRY_BITS; @@ -71,7 +72,7 @@ module tlb_cam #(parameter ENTRY_BITS = 3, // In case there are multiple matches in the CAM, select only one // *** it might be guaranteed that the CAM will never have multiple matches. // If so, this is just an encoder - priority_encoder #(ENTRY_BITS) match_priority(Matches, VPNIndex); + priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex); assign CAMHit = |Matches & ~TLBFlush; assign HitPageType = PageTypeList[VPNIndex]; diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlb_ram.sv index 9c281d2d..354e2a73 100644 --- a/wally-pipelined/src/mmu/tlb_ram.sv +++ b/wally-pipelined/src/mmu/tlb_ram.sv @@ -28,12 +28,13 @@ `include "wally-config.vh" `include "wally-constants.vh" -module tlb_ram #(parameter ENTRY_BITS = 3) ( - input clk, reset, - input [ENTRY_BITS-1:0] VPNIndex, // Index to read from - input [ENTRY_BITS-1:0] WriteIndex, - input [`XLEN-1:0] PageTableEntryWrite, - input TLBWrite, +module tlbram #(parameter ENTRY_BITS = 3) ( + input logic clk, reset, + input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from +// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused? + input logic [`XLEN-1:0] PTEWriteVal, + input logic TLBWrite, + input logic [2**ENTRY_BITS-1:0] WriteLines, output [`PPN_BITS-1:0] PhysicalPageNumber, output [7:0] PTEAccessBits @@ -51,9 +52,9 @@ module tlb_ram #(parameter ENTRY_BITS = 3) ( // Generate a flop for every entry in the RAM generate genvar i; - for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops - flopenr #(`XLEN) pte_flop(clk, reset, RAMEntryWrite[i] & TLBWrite, - PageTableEntryWrite, ram[i]); + for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops + flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite, + PTEWriteVal, ram[i]); end endgenerate