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Update synthesis script for overwrite during copy

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This commit is contained in:
James Stine 2022-02-03 20:29:03 -06:00
parent c3333150c3
commit dae826bd75
1 changed files with 5 additions and 5 deletions
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10
synthDC/scripts/synth.tcl
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@ -6,11 +6,11 @@
# Config # Config
set hdl_src "../pipelined/src" set hdl_src "../pipelined/src"
eval file copy ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/}
eval file copy ${hdl_src}/../config/rv32e/wally-config.vh {reports/} eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/}
eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files # Verilog files
set my_verilog_files [glob hdl/*] set my_verilog_files [glob hdl/*]