From dae826bd75f06d77f417e1477a9519b45a7772d7 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 3 Feb 2022 20:29:03 -0600 Subject: [PATCH] Update synthesis script for overwrite during copy --- synthDC/scripts/synth.tcl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index e5b197b3..23a30593 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -6,11 +6,11 @@ # Config set hdl_src "../pipelined/src" -eval file copy ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} -eval file copy ${hdl_src}/../config/rv32e/wally-config.vh {reports/} -eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/} -eval file copy [glob ${hdl_src}/*/*.sv] {hdl/} -eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/} +eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} +eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} +eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} # Verilog files set my_verilog_files [glob hdl/*]