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Begin cleanup of ifu. partial move of pc muxes inside bp.

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This commit is contained in:
Ross Thompson 2022-12-19 22:46:11 -06:00
parent e4579f3e9b
commit d8ee0ea59d
2 changed files with 12 additions and 7 deletions
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14
pipelined/src/ifu/bpred.sv
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@ -41,8 +41,8 @@ module bpred
// the prediction // the prediction
input logic [31:0] InstrD, input logic [31:0] InstrD,
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
output logic [`XLEN-1:0] BPPredPCF, input logic [`XLEN-1:0] PCPlus2or4F,
output logic SelBPPredF, output logic [`XLEN-1:0] PCNext0F,
// Update Predictor // Update Predictor
input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
// 1 hot encoding // 1 hot encoding
@ -57,7 +57,7 @@ module bpred
output logic [4:0] InstrClassM, output logic [4:0] InstrClassM,
// Report branch prediction status // Report branch prediction status
output logic BPPredWrongE, output logic BPPredWrongE,
output logic BPPredWrongM, output logic BPPredWrongM,
output logic BPPredDirWrongM, output logic BPPredDirWrongM,
output logic BTBPredPCWrongM, output logic BTBPredPCWrongM,
output logic RASPredPCWrongM, output logic RASPredPCWrongM,
@ -76,6 +76,10 @@ module bpred
logic [4:0] InstrClassD, InstrClassE; logic [4:0] InstrClassD, InstrClassE;
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF;
// Part 1 branch direction prediction // Part 1 branch direction prediction
@ -250,4 +254,8 @@ module bpred
.OldState(BPPredE), .OldState(BPPredE),
.NewState(UpdateBPPredE)); .NewState(UpdateBPPredE));
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
endmodule endmodule

5
pipelined/src/ifu/ifu.sv
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@ -306,16 +306,13 @@ module ifu (
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
if (`BPRED_ENABLED) begin : bpred if (`BPRED_ENABLED) begin : bpred
logic BPPredWrongM; logic BPPredWrongM;
logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF;
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushD, .FlushE, .FlushM, .FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
// Mux only required on instruction class miss prediction. // Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate)); .s(BPPredWrongM), .y(PCBPWrongInvalidate));