diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index 908d9a6b..4e231282 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -41,8 +41,8 @@ module bpred
    // the prediction
    input logic [31:0]       InstrD, 
    input logic [`XLEN-1:0]  PCNextF, // *** forgot to include this one on the I/O list
-   output logic [`XLEN-1:0] BPPredPCF,
-   output logic             SelBPPredF,
+   input logic [`XLEN-1:0]  PCPlus2or4F,
+   output logic [`XLEN-1:0] PCNext0F,
    // Update Predictor
    input logic [`XLEN-1:0]  PCE, // The address of the currently executing instruction
    // 1 hot encoding
@@ -57,7 +57,7 @@ module bpred
    output logic [4:0]       InstrClassM,
    // Report branch prediction status
    output logic             BPPredWrongE,
-   output logic             BPPredWrongM,   
+   output logic             BPPredWrongM, 
    output logic             BPPredDirWrongM,
    output logic             BTBPredPCWrongM,
    output logic             RASPredPCWrongM,
@@ -76,6 +76,10 @@ module bpred
   logic [4:0]               InstrClassD, InstrClassE;
   logic                     BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
+  logic                     SelBPPredF;
+  logic [`XLEN-1:0]         BPPredPCF;
+  
+  
 
   // Part 1 branch direction prediction
 
@@ -250,4 +254,8 @@ module bpred
      .OldState(BPPredE),
      .NewState(UpdateBPPredE));
 
+
+  mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
+  
+
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index ce63a6c9..d6640a6c 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -306,16 +306,13 @@ module ifu (
   ////////////////////////////////////////////////////////////////////////////////////////////////
   if (`BPRED_ENABLED) begin : bpred
     logic                        BPPredWrongM;
-    logic                        SelBPPredF;
-    logic [`XLEN-1:0]            BPPredPCF;
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, 
                 .FlushD, .FlushE, .FlushM,
-                .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
+                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, 
                 .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
 
-    mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
     // Mux only required on instruction class miss prediction.
     mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), 
                                               .s(BPPredWrongM), .y(PCBPWrongInvalidate));