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Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed.

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Ross Thompson 2023-04-18 17:45:41 -05:00
parent bb4ebd9b61
commit d783456746
1 changed files with 1 additions and 1 deletions
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2
fpga/src/fpgaTopArtyA7.v
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@ -354,7 +354,7 @@ module fpgaTop
.s_axi_rready(m_axi_rready), .s_axi_rready(m_axi_rready),
.m_axi_aclk(BUSCLK), .m_axi_aclk(BUSCLK),
.m_axi_aresetn(~resetn), .m_axi_aresetn(resetn),
.m_axi_awid(BUS_axi_awid), .m_axi_awid(BUS_axi_awid),
.m_axi_awlen(BUS_axi_awlen), .m_axi_awlen(BUS_axi_awlen),
.m_axi_awsize(BUS_axi_awsize), .m_axi_awsize(BUS_axi_awsize),