From d7834567462221ca7957e9eaa59428c61114410b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Apr 2023 17:45:41 -0500 Subject: [PATCH] Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. --- fpga/src/fpgaTopArtyA7.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v index c0e39c1a..e9ef06be 100644 --- a/fpga/src/fpgaTopArtyA7.v +++ b/fpga/src/fpgaTopArtyA7.v @@ -354,7 +354,7 @@ module fpgaTop .s_axi_rready(m_axi_rready), .m_axi_aclk(BUSCLK), - .m_axi_aresetn(~resetn), + .m_axi_aresetn(resetn), .m_axi_awid(BUS_axi_awid), .m_axi_awlen(BUS_axi_awlen), .m_axi_awsize(BUS_axi_awsize),