From d2d528cf3ce7532a625c2d56c00afe673611e5f3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 10 Apr 2023 14:36:33 -0500
Subject: [PATCH] Finally building ddr3 xilinx ip from script.

---
 fpga/generator/Makefile             | 13 +++++++------
 fpga/generator/xlnx_ddr3-artya7.tcl |  2 +-
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 1d07305f..2360760c 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -1,14 +1,14 @@
 dst := IP
 sdc_src := ~/repos/sdc.tar.gz
 # vcu118
-#export XILINX_PART := xcvu9p-flga2104-2L-e
-#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
-#export board := vcu118
+export XILINX_PART := xcvu9p-flga2104-2L-e
+export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
+export board := vcu118
 
 # vcu108
-export XILINX_PART := xcvu095-ffva2104-2-e
-export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
-export board := vcu108
+#export XILINX_PART := xcvu095-ffva2104-2-e
+#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
+#export board := vcu108
 
 
 all: FPGA
@@ -18,6 +18,7 @@ FPGA: PreProcessFiles IP SDC
 
 IP: $(dst)/xlnx_proc_sys_reset.log \
 	$(dst)/xlnx_ddr4-$(board).log \
+	$(dst)/xlnx_ddr3-artya7.log \
 	$(dst)/xlnx_axi_clock_converter.log \
 	 $(dst)/xlnx_ahblite_axi_bridge.log
 
diff --git a/fpga/generator/xlnx_ddr3-artya7.tcl b/fpga/generator/xlnx_ddr3-artya7.tcl
index 25d0af0d..eabad812 100644
--- a/fpga/generator/xlnx_ddr3-artya7.tcl
+++ b/fpga/generator/xlnx_ddr3-artya7.tcl
@@ -17,7 +17,7 @@ create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
 # 4. Then reconstruct the list with the needed parameters.
 # turns out the ddr3 mig cannot be built this way like the ddr 4 mig?!?!?
 # instead we need to read the project file, but we have to copy it to the corret location first
-cp $WALLY/fpga/generator/xlnx_ddr3-artya7-mig.prj IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/
+exec cp ../xlnx_ddr3-artya7-mig.prj xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/
 
 # unlike the vertex ultra scale and ultra scale + fpga's the atrix 7 mig we only get ui clock.