forked from Github_Repos/cvw
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
This commit is contained in:
parent
ea84211ff9
commit
d21be9d998
@ -124,3 +124,5 @@
|
|||||||
`define BPRED_ENABLED 1
|
`define BPRED_ENABLED 1
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -130,3 +130,5 @@
|
|||||||
`define BPRED_ENABLED 1
|
`define BPRED_ENABLED 1
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 1
|
`define TESTSBP 1
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -127,3 +127,5 @@
|
|||||||
`define BPRED_ENABLED 0
|
`define BPRED_ENABLED 0
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -126,3 +126,5 @@
|
|||||||
`define BPRED_ENABLED 1
|
`define BPRED_ENABLED 1
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -126,3 +126,5 @@
|
|||||||
`define BPRED_ENABLED 1
|
`define BPRED_ENABLED 1
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -126,3 +126,5 @@
|
|||||||
`define BPRED_ENABLED 1
|
`define BPRED_ENABLED 1
|
||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -129,3 +129,5 @@
|
|||||||
//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
|
//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE
|
||||||
`define TESTSBP 1
|
`define TESTSBP 1
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -130,3 +130,4 @@
|
|||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
@ -130,3 +130,4 @@
|
|||||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||||
`define TESTSBP 0
|
`define TESTSBP 0
|
||||||
|
|
||||||
|
`define REPLAY 0
|
||||||
|
6
pipelined/src/cache/cache.sv
vendored
6
pipelined/src/cache/cache.sv
vendored
@ -147,8 +147,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
|
|||||||
// There are two ways to resolve. 1. We can replay the read of the sram or we can save
|
// There are two ways to resolve. 1. We can replay the read of the sram or we can save
|
||||||
// the data. Replay is eaiser but creates a longer critical path.
|
// the data. Replay is eaiser but creates a longer critical path.
|
||||||
// save/restore only wayhit and readdata.
|
// save/restore only wayhit and readdata.
|
||||||
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved);
|
if(!`REPLAY) begin
|
||||||
mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit);
|
flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved);
|
||||||
|
mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit);
|
||||||
|
end else assign WayHit = WayHitRaw;
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// Write Path: Write Enables
|
// Write Path: Write Enables
|
||||||
|
25
pipelined/src/cache/cachefsm.sv
vendored
25
pipelined/src/cache/cachefsm.sv
vendored
@ -181,8 +181,8 @@ module cachefsm
|
|||||||
|
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if (`REPLAY) PreSelAdr = 2'b01;
|
||||||
save = 1'b1;
|
else save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
SRAMWordWriteEnable = 1'b1;
|
SRAMWordWriteEnable = 1'b1;
|
||||||
@ -198,8 +198,8 @@ module cachefsm
|
|||||||
|
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if(`REPLAY) PreSelAdr = 2'b01;
|
||||||
save = 1'b1;
|
else save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -215,8 +215,8 @@ module cachefsm
|
|||||||
|
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if(`REPLAY) PreSelAdr = 2'b01;
|
||||||
save = 1'b1;
|
else save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -276,7 +276,6 @@ module cachefsm
|
|||||||
end
|
end
|
||||||
|
|
||||||
STATE_MISS_READ_WORD_DELAY: begin
|
STATE_MISS_READ_WORD_DELAY: begin
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
|
||||||
SRAMWordWriteEnable = 1'b0;
|
SRAMWordWriteEnable = 1'b0;
|
||||||
SetDirty = 1'b0;
|
SetDirty = 1'b0;
|
||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
@ -284,7 +283,7 @@ module cachefsm
|
|||||||
PreSelAdr = 2'b01;
|
PreSelAdr = 2'b01;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||||
save = 1'b1;
|
if(~`REPLAY) save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
SRAMWordWriteEnable = 1'b1;
|
SRAMWordWriteEnable = 1'b1;
|
||||||
@ -296,8 +295,8 @@ module cachefsm
|
|||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if(`REPLAY) PreSelAdr = 2'b01;
|
||||||
save = 1'b1;
|
else save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -312,8 +311,8 @@ module cachefsm
|
|||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if(`REPLAY) PreSelAdr = 2'b01;
|
||||||
save = 1'b1;
|
else save = 1'b1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
@ -337,7 +336,7 @@ module cachefsm
|
|||||||
restore = 1'b1;
|
restore = 1'b1;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
//PreSelAdr = 2'b01; `REPLAY
|
if(`REPLAY) PreSelAdr = 2'b01;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
9
pipelined/src/cache/subcachelineread.sv
vendored
9
pipelined/src/cache/subcachelineread.sv
vendored
@ -61,8 +61,9 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
|
|||||||
end
|
end
|
||||||
// variable input mux
|
// variable input mux
|
||||||
assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]];
|
assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]];
|
||||||
flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
|
if(!`REPLAY) begin
|
||||||
mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
|
flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved);
|
||||||
restore, ReadDataWord);
|
mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved,
|
||||||
|
restore, ReadDataWord);
|
||||||
|
end else assign ReadDataWord = ReadDataWordRaw;
|
||||||
endmodule
|
endmodule
|
||||||
|
Loading…
Reference in New Issue
Block a user