From d21be9d9986a8202136e3fc8adc970cf8c8e3da4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 4 Feb 2022 23:19:00 -0600 Subject: [PATCH] Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. --- pipelined/config/buildroot/wally-config.vh | 2 ++ pipelined/config/fpga/wally-config.vh | 2 ++ pipelined/config/rv32etim/wally-config.vh | 2 ++ pipelined/config/rv32gc/wally-config.vh | 2 ++ pipelined/config/rv32ic/wally-config.vh | 2 ++ pipelined/config/rv32tim/wally-config.vh | 2 ++ pipelined/config/rv64BP/wally-config.vh | 2 ++ pipelined/config/rv64gc/wally-config.vh | 1 + pipelined/config/rv64ic/wally-config.vh | 1 + pipelined/src/cache/cache.sv | 6 ++++-- pipelined/src/cache/cachefsm.sv | 25 +++++++++++----------- pipelined/src/cache/subcachelineread.sv | 9 ++++---- 12 files changed, 37 insertions(+), 19 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index f879ce2a..1bdea74a 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -124,3 +124,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 58efd046..223aa3d8 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -130,3 +130,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 1 + +`define REPLAY 0 diff --git a/pipelined/config/rv32etim/wally-config.vh b/pipelined/config/rv32etim/wally-config.vh index bbeccbe8..4f77ae8b 100644 --- a/pipelined/config/rv32etim/wally-config.vh +++ b/pipelined/config/rv32etim/wally-config.vh @@ -127,3 +127,5 @@ `define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index a3859740..af6ef40c 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -126,3 +126,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index d0b8adfb..4d7b0418 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -126,3 +126,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32tim/wally-config.vh b/pipelined/config/rv32tim/wally-config.vh index 0fb1dafa..713a6a6b 100644 --- a/pipelined/config/rv32tim/wally-config.vh +++ b/pipelined/config/rv32tim/wally-config.vh @@ -126,3 +126,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 78230552..f8ee8903 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -129,3 +129,5 @@ //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE `define TESTSBP 1 + +`define REPLAY 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index f5bc8a29..ea17620c 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -130,3 +130,4 @@ `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define REPLAY 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 00b9a87f..ec497db2 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -130,3 +130,4 @@ `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define REPLAY 0 diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index b2e6d239..4c8f88aa 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -147,8 +147,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // There are two ways to resolve. 1. We can replay the read of the sram or we can save // the data. Replay is eaiser but creates a longer critical path. // save/restore only wayhit and readdata. - flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved); - mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit); + if(!`REPLAY) begin + flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved); + mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit); + end else assign WayHit = WayHitRaw; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 3b60efe1..75bcb266 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -181,8 +181,8 @@ module cachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; - //PreSelAdr = 2'b01; `REPLAY - save = 1'b1; + if (`REPLAY) PreSelAdr = 2'b01; + else save = 1'b1; end else begin SRAMWordWriteEnable = 1'b1; @@ -198,8 +198,8 @@ module cachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - //PreSelAdr = 2'b01; `REPLAY - save = 1'b1; + if(`REPLAY) PreSelAdr = 2'b01; + else save = 1'b1; end else begin NextState = STATE_READY; @@ -215,8 +215,8 @@ module cachefsm if(CPUBusy) begin NextState = STATE_CPU_BUSY; - //PreSelAdr = 2'b01; `REPLAY - save = 1'b1; + if(`REPLAY) PreSelAdr = 2'b01; + else save = 1'b1; end else begin NextState = STATE_READY; @@ -276,7 +276,6 @@ module cachefsm end STATE_MISS_READ_WORD_DELAY: begin - //PreSelAdr = 2'b01; `REPLAY SRAMWordWriteEnable = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; @@ -284,7 +283,7 @@ module cachefsm PreSelAdr = 2'b01; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; - save = 1'b1; + if(~`REPLAY) save = 1'b1; end else begin SRAMWordWriteEnable = 1'b1; @@ -296,8 +295,8 @@ module cachefsm LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - //PreSelAdr = 2'b01; `REPLAY - save = 1'b1; + if(`REPLAY) PreSelAdr = 2'b01; + else save = 1'b1; end else begin NextState = STATE_READY; @@ -312,8 +311,8 @@ module cachefsm LRUWriteEn = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - //PreSelAdr = 2'b01; `REPLAY - save = 1'b1; + if(`REPLAY) PreSelAdr = 2'b01; + else save = 1'b1; end else begin NextState = STATE_READY; @@ -337,7 +336,7 @@ module cachefsm restore = 1'b1; if(CPUBusy) begin NextState = STATE_CPU_BUSY; - //PreSelAdr = 2'b01; `REPLAY + if(`REPLAY) PreSelAdr = 2'b01; end else begin NextState = STATE_READY; diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index e42f5e71..111ec506 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -61,8 +61,9 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( end // variable input mux assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]]; - flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); - mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, - restore, ReadDataWord); - + if(!`REPLAY) begin + flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); + mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, + restore, ReadDataWord); + end else assign ReadDataWord = ReadDataWordRaw; endmodule