From c479b9f1120f329db0a571d90ebe09343fc03a1d Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 21 Dec 2022 19:35:47 +0000 Subject: [PATCH 1/2] fixed normshift calculations --- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index ca82c4f8..8190b317 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -127,10 +127,10 @@ module fdivsqrtpostproc( always_comb if (RemOpM) begin - NormShiftM = (m + (`DIVBLEN)'(`DIVa)); + NormShiftM = (m + (`DIVBLEN+1)'(`DIVa)); PreResultM = IntRemM; end else begin - NormShiftM = ((`DIVBLEN)'(`DIVb) - (n << `LOGR)); + NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (n << `LOGR)); PreResultM = {3'b000, IntQuotM}; end From b7224cc5baad3079a0aa793a4cb84e68cb0d771b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 14:50:01 -0600 Subject: [PATCH 2/2] Updated fpga constraints. --- fpga/constraints/debug2.xdc | 2 +- fpga/generator/Makefile | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 07eab1ae..480575aa 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -316,7 +316,7 @@ connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IF create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 8dff84a4..f39a9bce 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,13 +1,13 @@ dst := IP # vcu118 -#export XILINX_PART := xcvu9p-flga2104-2L-e -#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -#export board := vcu118 +export XILINX_PART := xcvu9p-flga2104-2L-e +export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +export board := vcu118 # vcu108 -export XILINX_PART := xcvu095-ffva2104-2-e -export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -export board := vcu108 +#export XILINX_PART := xcvu095-ffva2104-2-e +#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +#export board := vcu108 all: FPGA