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busybear: stop NOPing out atomics

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and bump regression to check for 800k instrs, up from 200k
This commit is contained in:
Noah Boorstin 2021-03-25 13:29:16 -04:00
parent ee36f4e09b
commit d02c88dab5
3 changed files with 5 additions and 28 deletions
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1
.gitignore vendored
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@ -15,3 +15,4 @@ wlft*
/imperas-riscv-tests/FunctionRadix_64.addr
/imperas-riscv-tests/FunctionRadix.addr
/imperas-riscv-tests/ProgramMap.txt
/wally-pipelined/busybear-testgen/gdbcombined.txt

2
wally-pipelined/regression/regression-wally.py
View File

@ -28,7 +28,7 @@ def test_config(config, print_res=True):
cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname
os.system(cmd)
# check for success. grep returns 0 if found, 1 if not found
passed = search_log_for_text("# loaded 200000 instructions", logname)
passed = search_log_for_text("# loaded 800000 instructions", logname)
else:
# Any other configuration loads that name from the config folder and runs vsim
cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n"

30
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -192,7 +192,7 @@ module testbench_busybear();
always @(dut.HRDATA) begin
#1;
if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
if (dut.hart.MemRWM[1] && ~HWRITE && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
//$display("%0t", $time);
if($feof(data_file_memR)) begin
$display("no more memR data to read");
@ -402,19 +402,7 @@ module testbench_busybear();
forcedInstr = 1;
end
else begin
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
release CheckInstrF;
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
#7;
release dut.hart.ifu.InstrF;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
warningCount += 1;
forcedInstr = 1;
end
else begin
forcedInstr = 0;
end
forcedInstr = 0;
end
end
end
@ -441,19 +429,7 @@ module testbench_busybear();
forcedInstr = 1;
end
else begin
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
release CheckInstrF;
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
#7;
release dut.hart.ifu.InstrF;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
warningCount += 1;
forcedInstr = 1;
end
else begin
forcedInstr = 0;
end
forcedInstr = 0;
end
end
// then expected PC value