diff --git a/.gitignore b/.gitignore
index 8c40fe78..db83fd6b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,3 +15,4 @@ wlft*
 /imperas-riscv-tests/FunctionRadix_64.addr
 /imperas-riscv-tests/FunctionRadix.addr
 /imperas-riscv-tests/ProgramMap.txt
+/wally-pipelined/busybear-testgen/gdbcombined.txt
diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 0ea10e5c..a352c375 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -28,7 +28,7 @@ def test_config(config, print_res=True):
     cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname
     os.system(cmd)
     # check for success.  grep returns 0 if found, 1 if not found
-    passed = search_log_for_text("# loaded 200000 instructions", logname)
+    passed = search_log_for_text("# loaded 800000 instructions", logname)
   else:
     # Any other configuration loads that name from the config folder and runs vsim
     cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n"
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index 6f957efa..0123bc7f 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -192,7 +192,7 @@ module testbench_busybear();
 
   always @(dut.HRDATA) begin
     #1;
-    if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
+    if (dut.hart.MemRWM[1] && ~HWRITE && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
       //$display("%0t", $time);
       if($feof(data_file_memR)) begin
         $display("no more memR data to read");
@@ -402,19 +402,7 @@ module testbench_busybear();
               forcedInstr = 1;
             end
             else begin
-              if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
-                force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
-                release CheckInstrF;
-                force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
-                #7;
-                release dut.hart.ifu.InstrF;
-                $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
-                warningCount += 1;
-                forcedInstr = 1;
-              end
-              else begin
-                forcedInstr = 0;
-              end
+              forcedInstr = 0;
             end
           end
         end
@@ -441,19 +429,7 @@ module testbench_busybear();
               forcedInstr = 1;
             end
             else begin
-              if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
-                force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
-                release CheckInstrF;
-                force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
-                #7;
-                release dut.hart.ifu.InstrF;
-                $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
-                warningCount += 1;
-                forcedInstr = 1;
-              end
-              else begin
-                forcedInstr = 0;
-              end
+              forcedInstr = 0;
             end
           end
           // then expected PC value