From cfd522da6b8ce4d5a6c9b26f3ad0b772967b58b4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 17 Sep 2021 10:33:57 -0500 Subject: [PATCH] The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. --- wally-pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index c5b078ed..0a16a8fd 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -78,7 +78,7 @@ module hazard( assign FlushF = BPPredWrongE | InvalidateICacheM; assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; - assign FlushM = FirstUnstalledM | TrapM | RetM; + assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM; // on Trap the memory stage should be flushed going into the W stage, // except if the instruction causing the Trap is an ecall or ebreak. assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));