forked from Github_Repos/cvw
Now reports if there is a hit or miss.
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@ -568,11 +568,13 @@ end
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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string HitMissString;
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assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : "M";
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
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if(Enable) begin // only log i cache reads
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$fwrite(file, "%h R\n", dut.core.ifu.PCPF);
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$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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@ -582,8 +584,10 @@ end
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int file;
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string LogFile;
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logic resetD, resetEdge;
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string HitMissString;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : "M";
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initial begin
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LogFile = $psprintf("DCache.log");
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file = $fopen(LogFile, "w");
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@ -594,13 +598,13 @@ end
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if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
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if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin
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$fwrite(file, "%h R\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h R %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin
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$fwrite(file, "%h W\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h W %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change
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$fwrite(file, "%h A\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h A %s\n", dut.core.lsu.PAdrM, HitMissString);
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end else if (dut.core.lsu.bus.dcache.FlushDCache) begin
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$fwrite(file, "%h F\n", dut.core.lsu.PAdrM);
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$fwrite(file, "%h F %s\n", dut.core.lsu.PAdrM, HitMissString);
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end
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end
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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