diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index c85f5d4f..9ac700bd 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -72,9 +72,19 @@ module wallypipelinedsoc (
   logic [31:0]      InstrF;
    
   // instantiate processor and memories
-  wallypipelinedhart hart(.*);
+  wallypipelinedhart hart(.clk, .reset,
+    .PCF,  .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, 
+    .MTIME_CLINT, .MTIMECMP_CLINT, .rd2, 
+    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
+    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
+    .HSELRegions, .HADDRD, .HSIZED, .HWRITED
+   );
 
   // instructions now come from uncore memory. This line can be removed at any time.
   // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
-  uncore uncore(.HWDATAIN(HWDATA), .*);
+  uncore uncore(.HCLK, .HRESETn,
+    .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
+    .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
+    .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .MTIMECMP_CLINT
+);
 endmodule
\ No newline at end of file