forked from Github_Repos/cvw
modified cnt for zbb to mux inputs
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@ -31,54 +31,50 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module cnt #(parameter WIDTH = 32) (
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module cnt #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, // Operand
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input logic [WIDTH-1:0] A, B, // Operands
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input logic W64, // Indicates word operation
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input logic W64, // Indicates word operation
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output logic [WIDTH-1:0] clzResult, // leading zeros result
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output logic [WIDTH-1:0] czResult, // count zeros result
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output logic [WIDTH-1:0] ctzResult, // trailing zeros result
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output logic [WIDTH-1:0] cpopResult);// population count result
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output logic [WIDTH-1:0] cpopResult);// population count result
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//count instructions
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//count instructions
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logic [WIDTH-1:0] clzA, clzB;
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logic [WIDTH-1:0] lzcA, popcntA;
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logic [WIDTH-1:0] clzwA, clzwB;
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logic [WIDTH-1:0] revA;
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logic [WIDTH-1:0] ctzA, ctzB;
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logic [WIDTH-1:0] ctzwA, ctzwB;
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logic [WIDTH-1:0] cpopwA, cpopA;
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logic [WIDTH-1:0] cpopwB, cpopB;
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//in both rv64, rv32
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//in both rv64, rv32
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assign clzA = A;
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bitreverse #(WIDTH) brtz(.a(A), .b(revA));
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bitreverse #(WIDTH) brtz(.a(A), .b(ctzA));
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//only in rv64
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//only in rv64
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if (WIDTH==64) begin
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if (WIDTH==64) begin
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assign clzwA = {A[31:0],{32{1'b1}}};
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//NOTE: signal widths can be decreased
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bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA));
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always_comb begin
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assign cpopwA = {{32{1'b0}},A};
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//clz input select mux
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case({B,W64})
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5'b00000_0: lzcA = A; //clz
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5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw
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5'b00001_0: lzcA = revA; //ctz
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5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw
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endcase
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//cpop select mux
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case ({B,W64})
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5'b00010_0: popcntA = A;
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5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]};
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endcase
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end
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end
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end
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else begin
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else begin
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assign clzwA = 32'b0;
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assign popcntA = A;
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assign ctzwA = 32'b0;
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always_comb begin
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assign cpopwA = 32'b0;
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//clz input slect mux
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case(B)
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5'b00000: lzcA = A;
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5'b00001: lzcA = revA;
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endcase
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end
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end
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end
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//NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later.
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//NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later.
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//NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later.
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lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB));
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lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult));
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lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB));
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popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult));
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lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB));
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lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB));
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popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB));
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popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB));
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if (WIDTH==64) begin
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assign clzResult = W64 ? clzwB : clzB;
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assign ctzResult = W64 ? ctzwB : ctzB;
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assign cpopResult = W64 ? cpopwB : cpopB;
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end
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else begin
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assign clzResult = clzB;
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assign ctzResult = ctzB;
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assign cpopResult = cpopB;
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end
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endmodule
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endmodule
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