From ce9dca8aecbd0490a48e40af236d638b98bef7c5 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Thu, 9 Feb 2023 16:45:22 +0000
Subject: [PATCH] modified cnt for zbb to mux inputs

---
 src/ieu/bmu/cnt.sv | 66 ++++++++++++++++++++++------------------------
 1 file changed, 31 insertions(+), 35 deletions(-)

diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv
index 84a30fc5..b0c44e06 100644
--- a/src/ieu/bmu/cnt.sv
+++ b/src/ieu/bmu/cnt.sv
@@ -31,54 +31,50 @@
 `include "wally-config.vh"
 
 module cnt #(parameter WIDTH = 32) (
-  input  logic [WIDTH-1:0] A,          // Operand
+  input  logic [WIDTH-1:0] A, B,        // Operands
   input  logic W64,                    // Indicates word operation
-  output logic [WIDTH-1:0] clzResult,  // leading zeros result
-  output logic [WIDTH-1:0] ctzResult,  // trailing zeros result
+  output logic [WIDTH-1:0] czResult,   // count zeros result
   output logic [WIDTH-1:0] cpopResult);// population count result
+
   //count instructions
-  logic [WIDTH-1:0] clzA, clzB;
-  logic [WIDTH-1:0] clzwA, clzwB;
-  logic [WIDTH-1:0] ctzA, ctzB;
-  logic [WIDTH-1:0] ctzwA, ctzwB;
-  logic [WIDTH-1:0] cpopwA, cpopA;
-  logic [WIDTH-1:0] cpopwB, cpopB;
+  logic [WIDTH-1:0] lzcA, popcntA;
+  logic [WIDTH-1:0] revA;
 
   //in both rv64, rv32
-  assign clzA = A;
-  bitreverse #(WIDTH) brtz(.a(A), .b(ctzA));
+  bitreverse #(WIDTH) brtz(.a(A), .b(revA));
   
   //only in rv64
   if (WIDTH==64) begin
-    assign clzwA = {A[31:0],{32{1'b1}}};
-    bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA));
-    assign cpopwA = {{32{1'b0}},A};
+    //NOTE: signal widths can be decreased
+    always_comb begin
+      //clz input select mux
+      case({B,W64})
+        5'b00000_0: lzcA = A;                       //clz
+        5'b00000_1: lzcA = {A[31:0],{32{1'b1}}};    //clzw
+        5'b00001_0: lzcA = revA;                    //ctz
+        5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw
+      endcase 
 
+      //cpop select mux
+      case ({B,W64})
+        5'b00010_0: popcntA = A;
+        5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]};
+      endcase
+    end
   end
   else begin
-    assign clzwA = 32'b0;
-    assign ctzwA = 32'b0;
-    assign cpopwA = 32'b0;
+    assign popcntA = A;
+    always_comb begin
+      //clz input slect mux
+      case(B)
+        5'b00000: lzcA = A;
+        5'b00001: lzcA = revA;
+      endcase
+    end
   end
 
-  //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later.
   //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later.
-  lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB));
-  lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB));
-  lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB));
-  lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB));
+  lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult));
+  popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult));
 
-  popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB));
-  popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB));
-
-  if (WIDTH==64) begin
-    assign clzResult = W64 ? clzwB : clzB;
-    assign ctzResult = W64 ? ctzwB : ctzB;
-    assign cpopResult = W64 ? cpopwB : cpopB;
-  end
-  else begin
-    assign clzResult = clzB;
-    assign ctzResult = ctzB;
-    assign cpopResult = cpopB;
-  end
 endmodule
\ No newline at end of file