modified cnt for zbb to mux inputs

This commit is contained in:
Kevin Kim 2023-02-09 16:45:22 +00:00
parent 95ff9e91c5
commit ce9dca8aec

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@ -31,54 +31,50 @@
`include "wally-config.vh" `include "wally-config.vh"
module cnt #(parameter WIDTH = 32) ( module cnt #(parameter WIDTH = 32) (
input logic [WIDTH-1:0] A, // Operand input logic [WIDTH-1:0] A, B, // Operands
input logic W64, // Indicates word operation input logic W64, // Indicates word operation
output logic [WIDTH-1:0] clzResult, // leading zeros result output logic [WIDTH-1:0] czResult, // count zeros result
output logic [WIDTH-1:0] ctzResult, // trailing zeros result
output logic [WIDTH-1:0] cpopResult);// population count result output logic [WIDTH-1:0] cpopResult);// population count result
//count instructions //count instructions
logic [WIDTH-1:0] clzA, clzB; logic [WIDTH-1:0] lzcA, popcntA;
logic [WIDTH-1:0] clzwA, clzwB; logic [WIDTH-1:0] revA;
logic [WIDTH-1:0] ctzA, ctzB;
logic [WIDTH-1:0] ctzwA, ctzwB;
logic [WIDTH-1:0] cpopwA, cpopA;
logic [WIDTH-1:0] cpopwB, cpopB;
//in both rv64, rv32 //in both rv64, rv32
assign clzA = A; bitreverse #(WIDTH) brtz(.a(A), .b(revA));
bitreverse #(WIDTH) brtz(.a(A), .b(ctzA));
//only in rv64 //only in rv64
if (WIDTH==64) begin if (WIDTH==64) begin
assign clzwA = {A[31:0],{32{1'b1}}}; //NOTE: signal widths can be decreased
bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); always_comb begin
assign cpopwA = {{32{1'b0}},A}; //clz input select mux
case({B,W64})
5'b00000_0: lzcA = A; //clz
5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw
5'b00001_0: lzcA = revA; //ctz
5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw
endcase
//cpop select mux
case ({B,W64})
5'b00010_0: popcntA = A;
5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]};
endcase
end
end end
else begin else begin
assign clzwA = 32'b0; assign popcntA = A;
assign ctzwA = 32'b0; always_comb begin
assign cpopwA = 32'b0; //clz input slect mux
case(B)
5'b00000: lzcA = A;
5'b00001: lzcA = revA;
endcase
end
end end
//NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later.
//NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later.
lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult));
lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult));
lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB));
lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB));
popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB));
popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB));
if (WIDTH==64) begin
assign clzResult = W64 ? clzwB : clzB;
assign ctzResult = W64 ? ctzwB : ctzB;
assign cpopResult = W64 ? cpopwB : cpopB;
end
else begin
assign clzResult = clzB;
assign ctzResult = ctzB;
assign cpopResult = cpopB;
end
endmodule endmodule