diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv
index e672a769..e3b22a86 100644
--- a/wally-pipelined/src/uncore/clint.sv
+++ b/wally-pipelined/src/uncore/clint.sv
@@ -27,23 +27,30 @@
`include "wally-config.vh"
module clint (
- input logic HCLK, HRESETn,
- input logic HSELCLINT,
- input logic [15:0] HADDR,
- input logic HWRITE,
- input logic [`XLEN-1:0] HWDATA,
+ input logic HCLK, HRESETn,
+ input logic HSELCLINT,
+ input logic [15:0] HADDR,
+ input logic HWRITE,
+ input logic [`XLEN-1:0] HWDATA,
output logic [`XLEN-1:0] HREADCLINT,
- output logic HRESPCLINT, HREADYCLINT,
- output logic TimerIntM, SwIntM);
+ output logic HRESPCLINT, HREADYCLINT,
+ input logic HREADY,
+ input logic [1:0] HTRANS,
+ output logic TimerIntM, SwIntM);
logic [63:0] MTIMECMP, MTIME;
logic MSIP;
- logic [15:0] entry;
+ logic [15:0] entry, entryd;
logic memread, memwrite;
+ logic initTrans;
+
+ assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
+ assign memread = initTrans & ~HWRITE;
+ // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
+ flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
+ flopr #(16) entrydflop(HCLK, ~HRESETn, entry, entryd);
- assign memread = HSELCLINT & ~HWRITE;
- assign memwrite = HSELCLINT & HWRITE;
assign HRESPCLINT = 0; // OK
assign HREADYCLINT = 1'b1; // will need to be modified if CLINT ever needs more than 1 cycle to do something
@@ -75,16 +82,22 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
- MTIME <= 0;
MTIMECMP <= 0;
// MTIMECMP is not reset
end else if (memwrite) begin
- if (entry == 16'h0000) MSIP <= HWDATA[0];
- if (entry == 16'h4000) MTIMECMP <= HWDATA;
+ if (entryd == 16'h0000) MSIP <= HWDATA[0];
+ if (entryd == 16'h4000) MTIMECMP <= HWDATA;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
- if (entry == 16'hBFF8) MTIME <= HWDATA;
- else MTIME <= MTIME + 1;
end
+
+ always_ff @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) begin
+ MTIME <= 0;
+ // MTIMECMP is not reset
+ end else if (memwrite && entryd == 16'hBFF8) begin
+ // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
+ MTIME <= HWDATA;
+ end else MTIME <= MTIME + 1;
end else begin // 32-bit
always @(posedge HCLK) begin
case(entry)
@@ -99,18 +112,25 @@ module clint (
always_ff @(posedge HCLK or negedge HRESETn)
if (~HRESETn) begin
MSIP <= 0;
- MTIME <= 0;
MTIMECMP <= 0;
// MTIMECMP is not reset
end else if (memwrite) begin
- if (entry == 16'h0000) MSIP <= HWDATA[0];
- if (entry == 16'h4000) MTIMECMP[31:0] <= HWDATA;
- if (entry == 16'h4004) MTIMECMP[63:32] <= HWDATA;
+ if (entryd == 16'h0000) MSIP <= HWDATA[0];
+ if (entryd == 16'h4000) MTIMECMP[31:0] <= HWDATA;
+ if (entryd == 16'h4004) MTIMECMP[63:32] <= HWDATA;
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
- if (entry == 16'hBFF8) MTIME[31:0] <= HWDATA;
- else if (entry == 16'hBFFC) MTIME[63:32]<= HWDATA;
- else MTIME <= MTIME + 1;
- end
+ end
+
+ always_ff @(posedge HCLK or negedge HRESETn)
+ if (~HRESETn) begin
+ MTIME <= 0;
+ // MTIMECMP is not reset
+ end else if (memwrite && (entryd == 16'hBFF8)) begin
+ MTIME[31:0] <= HWDATA;
+ end else if (memwrite && (entryd == 16'hBFFC)) begin
+ // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
+ MTIME[63:32]<= HWDATA;
+ end else MTIME <= MTIME + 1;
end
endgenerate
diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
index 409564f7..0bca336c 100644
--- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py
+++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
@@ -503,9 +503,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
- csrrc x28, mstatus, x1
+ csrrc x31, mstatus, x1
li x1, 0b0100000000000
- csrrs x28, mstatus, x1
+ csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@@ -520,7 +520,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
- csrrc x28, sstatus, x1
+ csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction
@@ -567,4 +567,4 @@ for xlen in xlens:
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()
- r.close()
\ No newline at end of file
+ r.close()
diff --git a/wally-pipelined/testgen/privileged/testgen-DELEG.py b/wally-pipelined/testgen/privileged/testgen-DELEG.py
index 4eecb53b..ab08d09d 100644
--- a/wally-pipelined/testgen/privileged/testgen-DELEG.py
+++ b/wally-pipelined/testgen/privileged/testgen-DELEG.py
@@ -233,9 +233,9 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
{beforeTest}
li x1, 0b110000000000
- csrrc x28, {testMode}status, x1
+ csrrc x31, {testMode}status, x1
li x1, 0b{"01" if mode == "s" else "00"}00000000000
- csrrs x28, {testMode}status, x1
+ csrrs x31, {testMode}status, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the ret instruction
diff --git a/wally-pipelined/testgen/privileged/testgen-EPC.py b/wally-pipelined/testgen/privileged/testgen-EPC.py
index 2fd0593b..8093ef40 100644
--- a/wally-pipelined/testgen/privileged/testgen-EPC.py
+++ b/wally-pipelined/testgen/privileged/testgen-EPC.py
@@ -210,9 +210,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
- csrrc x28, mstatus, x1
+ csrrc x31, mstatus, x1
li x1, 0b0100000000000
- csrrs x28, mstatus, x1
+ csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@@ -226,7 +226,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
- csrrc x28, sstatus, x1
+ csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction
@@ -260,4 +260,4 @@ for xlen in xlens:
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()
- r.close()
\ No newline at end of file
+ r.close()
diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/wally-pipelined/testgen/privileged/testgen-IE.py
index bb1ecd2c..5a82d019 100644
--- a/wally-pipelined/testgen/privileged/testgen-IE.py
+++ b/wally-pipelined/testgen/privileged/testgen-IE.py
@@ -346,9 +346,9 @@ for xlen in xlens:
# bring down to supervisor mode
lines += f"""
li x1, 0b110000000000
- csrrc x28, mstatus, x1
+ csrrc x31, mstatus, x1
li x1, 0b0100000000000
- csrrs x28, mstatus, x1
+ csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
diff --git a/wally-pipelined/testgen/privileged/testgen-TVAL.py b/wally-pipelined/testgen/privileged/testgen-TVAL.py
index 8a728f7a..572d930c 100644
--- a/wally-pipelined/testgen/privileged/testgen-TVAL.py
+++ b/wally-pipelined/testgen/privileged/testgen-TVAL.py
@@ -304,9 +304,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
- csrrc x28, mstatus, x1
+ csrrc x31, mstatus, x1
li x1, 0b0100000000000
- csrrs x28, mstatus, x1
+ csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@@ -321,7 +321,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
- csrrc x28, sstatus, x1
+ csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction
diff --git a/wally-pipelined/testgen/privileged/testgen-TVEC.py b/wally-pipelined/testgen/privileged/testgen-TVEC.py
index 8b731be8..fcdc80d7 100644
--- a/wally-pipelined/testgen/privileged/testgen-TVEC.py
+++ b/wally-pipelined/testgen/privileged/testgen-TVEC.py
@@ -406,9 +406,9 @@ for xlen in xlens:
if fromMode == "s" or fromMode == "u":
lines += f"""
li x1, 0b110000000000
- csrrc x28, mstatus, x1
+ csrrc x31, mstatus, x1
li x1, 0b0100000000000
- csrrs x28, mstatus, x1
+ csrrs x31, mstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the mret instruction
@@ -423,7 +423,7 @@ for xlen in xlens:
lines += f"""
li x1, 0b110000000000
- csrrc x28, sstatus, x1
+ csrrc x31, sstatus, x1
auipc x1, 0
addi x1, x1, 16 # x1 is now right after the sret instruction