Merge branch 'main' of https://github.com/openhwgroup/cvw

src/ieu/alu.sv

@@ -37,7 +37,7 @@ module alu #(parameter WIDTH=32) (
   input  logic [1:0]       BSelect,     // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
   input  logic [2:0]       ZBBSelect,   // ZBB mux select signal
   input  logic [2:0]       Funct3,      // For BMU decoding
-  input  logic [1:0]       CompFlags,   // Comparator flags
+  input  logic             CompLT,      // Less-Than flag from comparator
   input  logic [2:0]       BALUControl, // ALU Control signals for B instructions in Execute Stage
   output logic [WIDTH-1:0] Result,      // ALU result
   output logic [WIDTH-1:0] Sum);        // Sum of operands
@@ -90,7 +90,7 @@ module alu #(parameter WIDTH=32) (
   // Final Result B instruction select mux
   if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
     bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, 
-      .Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
+      .Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult,
       .CondMaskB, .CondShiftA, .Result);
   end else begin
     assign Result = ALUResult;

src/ieu/bmu/bitmanipalu.sv

@@ -35,7 +35,7 @@ module bitmanipalu #(parameter WIDTH=32) (
   input  logic [1:0]       BSelect,                 // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
   input  logic [2:0]       ZBBSelect,               // ZBB mux select signal
   input  logic [2:0]       Funct3,                  // Funct3 field of opcode indicates operation to perform
-  input  logic [1:0]       CompFlags,               // Comparator flags
+  input  logic             CompLT,                  // Less-Than flag from comparator
   input  logic [2:0]       BALUControl,             // ALU Control signals for B instructions in Execute Stage
   input  logic [WIDTH-1:0] ALUResult, FullResult,   // ALUResult, FullResult signals
   output logic [WIDTH-1:0] CondMaskB,               // B is conditionally masked for ZBS instructions
@@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) (
 
   // ZBB Unit
   if (`ZBB_SUPPORTED) begin: zbb
-    zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult);
+    zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult);
   end else assign ZBBResult = 0;
 
   // Result Select Mux

src/ieu/bmu/cnt.sv

@@ -32,7 +32,7 @@
 
 module cnt #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A, RevA,    // Operands
-  input  logic [4:0] B,                // Last 5 bits of immediate
+  input  logic [1:0] B,                // Last 2 bits of immediate
   input  logic W64,                    // Indicates word operation
   output logic [WIDTH-1:0] CntResult   // count result
 );

src/ieu/bmu/zbb.sv

@@ -32,10 +32,9 @@
 
 module zbb #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, RevA, B,   // Operands
-  input  logic [WIDTH-1:0] ALUResult,    // ALU Result
   input  logic             W64,          // Indicates word operation
   input  logic             lt,           // lt flag
-  input  logic [2:0]       ZBBSelect,    // Indicates word operation
+  input  logic [2:0]       ZBBSelect,    // ZBB Result select signal
   output logic [WIDTH-1:0] ZBBResult);   // ZBB result
   
   logic [WIDTH-1:0] CntResult;           // count result
@@ -43,7 +42,7 @@ module zbb #(parameter WIDTH=32) (
   logic [WIDTH-1:0] ByteResult;          // byte results
   logic [WIDTH-1:0] ExtResult;           // sign/zero extend results
 
-  cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult);
+  cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
   byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
   ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
 

src/ieu/datapath.sv

@@ -114,7 +114,7 @@ module datapath (
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
-  alu   #(`XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE);
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE);
   mux2 #(`XLEN)   altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
   mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
 

tests/coverage/priv.S

@@ -36,4 +36,11 @@ main:
     addi t0, zero, 0
     csrr t0, stimecmp 
 
+    # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
+    li t0, 0
+    csrw stval, t0
+    csrw scause, t0
+    csrw sepc, t0
+    csrw stimecmp, t0
+    
     j done