From b4d6021b3bfaac835692cbcfd231db7cb4a070ea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 26 Mar 2023 19:39:49 -0700 Subject: [PATCH 1/5] removed unneccesary input signal from zbb --- src/ieu/bmu/bitmanipalu.sv | 2 +- src/ieu/bmu/zbb.sv | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 07c7e534..4841f7dd 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) ( // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Result Select Mux diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 5d1c52f1..1dff2fd0 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,7 +32,6 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands - input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation From f3edbcea150234e7402530b9616dec7df2a5b8a9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 26 Mar 2023 20:06:55 -0700 Subject: [PATCH 2/5] removed unnecessary signal indices --- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 13ff1e15..75ace3ac 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -32,7 +32,7 @@ module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands - input logic [4:0] B, // Last 5 bits of immediate + input logic [1:0] B, // Last 2 bits of immediate input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1dff2fd0..fef8579b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -42,7 +42,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results - cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult); + cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); From adabb7c2363cfbd84c6a1808c7c3a2f9bcd3dc4a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Mar 2023 11:40:19 -0700 Subject: [PATCH 3/5] comment formatting --- src/ieu/bmu/zbb.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index fef8579b..a85114b5 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -34,11 +34,11 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic W64, // Indicates word operation input logic lt, // lt flag - input logic [2:0] ZBBSelect, // Indicates word operation + input logic [2:0] ZBBSelect, // ZBB Result select signal output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinMaxResult; // min,max result + logic [WIDTH-1:0] MinMaxResult; // min, max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results From 4fa2959e566780fa31544c6d77145174d127f84c Mon Sep 17 00:00:00 2001 From: Diego Herrera Vicioso Date: Tue, 28 Mar 2023 22:48:17 -0700 Subject: [PATCH 4/5] Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs. --- tests/coverage/priv.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 3aa3aea5..8cd18925 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,4 +36,11 @@ main: addi t0, zero, 0 csrr t0, stimecmp + # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs + li t0, 0 + csrw stval, t0 + csrw scause, t0 + csrw sepc, t0 + csrw stimecmp, t0 + j done From 97181e063b85107d0a3ed20b2496a4f3544f8a86 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 30 Mar 2023 19:15:33 -0700 Subject: [PATCH 5/5] only pass in relevant comparator flag to ALU --- src/ieu/alu.sv | 4 ++-- src/ieu/bmu/bitmanipalu.sv | 4 ++-- src/ieu/datapath.sv | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index c4e0f390..4db187e5 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,7 +37,7 @@ module alu #(parameter WIDTH=32) ( input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // For BMU decoding - input logic [1:0] CompFlags, // Comparator flags + input logic CompLT, // Less-Than flag from comparator input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -90,7 +90,7 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, - .Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult, + .Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4841f7dd..ae71db7b 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -35,7 +35,7 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform - input logic [1:0] CompFlags, // Comparator flags + input logic CompLT, // Less-Than flag from comparator input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions @@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) ( // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Result Select Mux diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index a48b3940..19d1264a 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -114,7 +114,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);