From c50a2bd8bf7704f62c1f9e9ed8e9d38ab15c28b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:51:35 -0600 Subject: [PATCH] Changed CPUBusy to Stall in ebu modules. --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/ebu/ahbcacheinterface.sv | 4 ++-- pipelined/src/ebu/ahbinterface.sv | 4 ++-- pipelined/src/ebu/buscachefsm.sv | 4 ++-- pipelined/src/ebu/busfsm.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 32112935..6c7aa899 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -35,7 +35,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic reset, // cpu side input logic FlushStage, - input logic CPUBusy, + input logic Stall, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, input logic FlushCache, @@ -194,7 +194,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .FlushStage, .CacheRW, .CacheAtomic, .CPUBusy, + .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 530cdb42..9c01b035 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -64,7 +64,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE input logic Flush, input logic [`PA_BITS-1:0] PAdr, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, input logic [2:0] Funct3, output logic SelBusBeat, output logic BusStall, @@ -114,7 +114,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( - .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, + .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index 9955cca5..0505cfc5 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -51,7 +51,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter input logic [1:0] BusRW, input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN-1:0] WriteData, - input logic CPUBusy, + input logic Stall, output logic BusStall, output logic BusCommitted, output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer); @@ -73,6 +73,6 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter end busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, - .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, + .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); endmodule diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index cddd7487..b89be641 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -40,7 +40,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, // IEU interface input logic Flush, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, output logic BusCommitted, output logic BusStall, output logic CaptureEn, @@ -89,7 +89,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, else NextState = ADR_PHASE; DATA_PHASE: if(HREADY) NextState = MEM3; else NextState = DATA_PHASE; - MEM3: if(CPUBusy) NextState = MEM3; + MEM3: if(Stall) NextState = MEM3; else NextState = ADR_PHASE; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 8203fa74..d2f9447e 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -38,7 +38,7 @@ module busfsm // IEU interface input logic Flush, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, output logic BusCommitted, output logic BusStall, output logic CaptureEn, @@ -65,7 +65,7 @@ module busfsm else NextState = ADR_PHASE; DATA_PHASE: if(HREADY) NextState = MEM3; else NextState = DATA_PHASE; - MEM3: if(CPUBusy) NextState = MEM3; + MEM3: if(Stall) NextState = MEM3; else NextState = ADR_PHASE; default: NextState = ADR_PHASE; endcase diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ba8ea190..f80d411e 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -243,7 +243,7 @@ module ifu ( .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .FetchBuffer, .PAdr(PCPF), - .BusRW, .CPUBusy, + .BusRW, .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF)); mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF), @@ -260,7 +260,7 @@ module ifu ( ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); + .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); assign CacheCommittedF = '0; if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 920a9a22..28860012 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -270,7 +270,7 @@ module lsu ( .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), - .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, + .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM)); // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. @@ -293,7 +293,7 @@ module lsu ( ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];