From c4f3f2f78372ef7f194b45541cacfc8d6f688d9c Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 24 May 2021 19:30:28 -0500 Subject: [PATCH] Minor cosmetic elements on div.sv --- wally-pipelined/src/muldiv/div.sv | 6 ------ 1 file changed, 6 deletions(-) diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 9d6d672d..db830ca3 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -130,7 +130,6 @@ module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start, S); // shifting N right by v+s so that (m+v+s) mod k = 0. And, // the quotient has to be aligned to the integer position. - // Actual divider unit FIXME: r16 (jes) divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, enable, otfzero, shiftResult); @@ -159,11 +158,6 @@ module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start, S); // RISC-V has exceptions for divide by 0 and overflow (see Table 6.1 of spec) exception_int exc (QT, remT, N, S, div0, Max_N, D_NegOne, Qf, remf); - // Delete me if works - // RISC-V has exceptions for divide by 0 (Table 6.1 of SPEC) - //mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf); - //mux2 #(64) exc2 (rem0, op1, div0, remf); - endmodule // int32div module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0,