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subword read and csrc lint cleanup

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This commit is contained in:
David Harris 2021-10-23 09:29:15 -07:00
parent 28d8f6d5cf
commit c316bff15a
2 changed files with 3 additions and 89 deletions
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82
wally-pipelined/src/lsu/subwordread.sv
View File

@ -32,9 +32,6 @@ module subwordread (
output logic [`XLEN-1:0] ReadDataM output logic [`XLEN-1:0] ReadDataM
); );
logic [7:0] ByteM;
logic [15:0] HalfwordM;
logic [`XLEN-1:0] offset0, offset1, offset2, offset3; logic [`XLEN-1:0] offset0, offset1, offset2, offset3;
// Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[2] is the unsigned bit. mask upper bits.
@ -42,8 +39,6 @@ module subwordread (
generate generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
// more complex solution, but faster
// 5 mux + 1 AND gate in series.
logic [`XLEN-1:0] offset4, offset5, offset6, offset7; logic [`XLEN-1:0] offset4, offset5, offset6, offset7;
always_comb always_comb
@ -95,56 +90,8 @@ module subwordread (
7: ReadDataM = offset7; 7: ReadDataM = offset7;
endcase endcase
// easier to understand but slower
// 8 muxes in series
/* -----\/----- EXCLUDED -----\/-----
// ByteMe mux
always_comb
case(MemPAdrM[2:0])
3'b000: ByteM = ReadDataWordMuxM[7:0];
3'b001: ByteM = ReadDataWordMuxM[15:8];
3'b010: ByteM = ReadDataWordMuxM[23:16];
3'b011: ByteM = ReadDataWordMuxM[31:24];
3'b100: ByteM = ReadDataWordMuxM[39:32];
3'b101: ByteM = ReadDataWordMuxM[47:40];
3'b110: ByteM = ReadDataWordMuxM[55:48];
3'b111: ByteM = ReadDataWordMuxM[63:56];
endcase
// halfword mux
always_comb
case(MemPAdrM[2:1])
2'b00: HalfwordM = ReadDataWordMuxM[15:0];
2'b01: HalfwordM = ReadDataWordMuxM[31:16];
2'b10: HalfwordM = ReadDataWordMuxM[47:32];
2'b11: HalfwordM = ReadDataWordMuxM[63:48];
endcase
logic [31:0] WordM;
always_comb
case(MemPAdrM[2])
1'b0: WordM = ReadDataWordMuxM[31:0];
1'b1: WordM = ReadDataWordMuxM[63:32];
endcase
// sign extension
always_comb
case({Funct3M[2], Funct3M[1:0]}) // Funct3M[2] indicates unsigned load
3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb
3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw
3'b011: ReadDataM = ReadDataWordMuxM; // ld
3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu
3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu
3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
endcase
-----/\----- EXCLUDED -----/\----- */
end else begin // 32-bit end else begin // 32-bit
// byte mux // byte mux
// fast but more complex
always_comb always_comb
case(Funct3M[1:0]) case(Funct3M[1:0])
3: offset0 = ReadDataWordMuxM; //ld illegal 3: offset0 = ReadDataWordMuxM; //ld illegal
@ -171,35 +118,6 @@ module subwordread (
2: ReadDataM = offset2; 2: ReadDataM = offset2;
3: ReadDataM = offset3; 3: ReadDataM = offset3;
endcase endcase
// slow but easier to understand
/* -----\/----- EXCLUDED -----\/-----
always_comb
case(MemPAdrM[1:0])
2'b00: ByteM = ReadDataWordMuxM[7:0];
2'b01: ByteM = ReadDataWordMuxM[15:8];
2'b10: ByteM = ReadDataWordMuxM[23:16];
2'b11: ByteM = ReadDataWordMuxM[31:24];
endcase
// halfword mux
always_comb
case(MemPAdrM[1])
1'b0: HalfwordM = ReadDataWordMuxM[15:0];
1'b1: HalfwordM = ReadDataWordMuxM[31:16];
endcase
// sign extension
always_comb
case({Funct3M[2], Funct3M[1:0]})
3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb
3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
3'b010: ReadDataM = ReadDataWordMuxM; // lw
3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu
3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu
default: ReadDataM = ReadDataWordMuxM;
endcase
-----/\----- EXCLUDED -----/\----- */
end end
endgenerate endgenerate
endmodule endmodule

4
wally-pipelined/src/privileged/csrc.sv
View File

@ -93,13 +93,9 @@ module csrc #(parameter
generate generate
if (`ZICOUNTERS_SUPPORTED) begin if (`ZICOUNTERS_SUPPORTED) begin
logic [63:0] CYCLE_REGW, INSTRET_REGW; logic [63:0] CYCLE_REGW, INSTRET_REGW;
logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired
logic [63:0] CYCLEPlusM, INSTRETPlusM; logic [63:0] CYCLEPlusM, INSTRETPlusM;
logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM;
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM; logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
logic WriteCYCLEM, WriteINSTRETM; logic WriteCYCLEM, WriteINSTRETM;
logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
logic [4:0] CounterNumM; logic [4:0] CounterNumM;
logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW; logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW;
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;