From c316bff15a37f1454e3107c20f2af461902a829e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 23 Oct 2021 09:29:15 -0700
Subject: [PATCH] subword read and csrc lint cleanup

---
 wally-pipelined/src/lsu/subwordread.sv | 84 +-------------------------
 wally-pipelined/src/privileged/csrc.sv |  8 +--
 2 files changed, 3 insertions(+), 89 deletions(-)

diff --git a/wally-pipelined/src/lsu/subwordread.sv b/wally-pipelined/src/lsu/subwordread.sv
index 50a205bf..1e975725 100644
--- a/wally-pipelined/src/lsu/subwordread.sv
+++ b/wally-pipelined/src/lsu/subwordread.sv
@@ -32,9 +32,6 @@ module subwordread (
   output logic [`XLEN-1:0] ReadDataM
 );
                   
-  logic [7:0]  ByteM; 
-  logic [15:0] HalfwordM;
-
   logic [`XLEN-1:0] offset0, offset1, offset2, offset3;
   
   // Funct3M[2] is the unsigned bit. mask upper bits.
@@ -42,8 +39,6 @@ module subwordread (
 
   generate
     if (`XLEN == 64) begin
-      // more complex solution, but faster
-      // 5 mux + 1 AND gate in series.
       logic [`XLEN-1:0] offset4, offset5, offset6, offset7;
 
       always_comb
@@ -95,56 +90,8 @@ module subwordread (
 	  7: ReadDataM = offset7;
 	endcase
 
-      // easier to understand but slower
-      // 8 muxes in series
-/* -----\/----- EXCLUDED -----\/-----
-      // ByteMe mux
-      always_comb
-      case(MemPAdrM[2:0])
-        3'b000: ByteM = ReadDataWordMuxM[7:0];
-        3'b001: ByteM = ReadDataWordMuxM[15:8];
-        3'b010: ByteM = ReadDataWordMuxM[23:16];
-        3'b011: ByteM = ReadDataWordMuxM[31:24];
-        3'b100: ByteM = ReadDataWordMuxM[39:32];
-        3'b101: ByteM = ReadDataWordMuxM[47:40];
-        3'b110: ByteM = ReadDataWordMuxM[55:48];
-        3'b111: ByteM = ReadDataWordMuxM[63:56];
-      endcase
-    
-      // halfword mux
-      always_comb
-      case(MemPAdrM[2:1])
-        2'b00: HalfwordM = ReadDataWordMuxM[15:0];
-        2'b01: HalfwordM = ReadDataWordMuxM[31:16];
-        2'b10: HalfwordM = ReadDataWordMuxM[47:32];
-        2'b11: HalfwordM = ReadDataWordMuxM[63:48];
-      endcase
-      
-      logic [31:0] WordM;
-      
-      always_comb
-        case(MemPAdrM[2])
-          1'b0: WordM = ReadDataWordMuxM[31:0];
-          1'b1: WordM = ReadDataWordMuxM[63:32];
-        endcase
-
-      // sign extension
-      always_comb
-      case({Funct3M[2], Funct3M[1:0]}) // Funct3M[2] indicates unsigned load
-        3'b000:  ReadDataM = {{56{ByteM[7]}}, ByteM};                  // lb
-        3'b001:  ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]};   // lh 
-        3'b010:  ReadDataM = {{32{WordM[31]}}, WordM[31:0]};           // lw
-        3'b011:  ReadDataM = ReadDataWordMuxM;                                   // ld
-        3'b100:  ReadDataM = {56'b0, ByteM[7:0]};                      // lbu
-        3'b101:  ReadDataM = {48'b0, HalfwordM[15:0]};                 // lhu
-        3'b110:  ReadDataM = {32'b0, WordM[31:0]};                     // lwu
-        default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
-      endcase
- -----/\----- EXCLUDED -----/\----- */
     end else begin // 32-bit
-      // byte mux
-
-      // fast but more complex
+     // byte mux
       always_comb
 	case(Funct3M[1:0])
 	  3: offset0 = ReadDataWordMuxM;                                                                 //ld  illegal
@@ -171,35 +118,6 @@ module subwordread (
 	  2: ReadDataM = offset2;
 	  3: ReadDataM = offset3;
 	endcase
-
-      // slow but easier to understand
-/* -----\/----- EXCLUDED -----\/-----
-      always_comb
-      case(MemPAdrM[1:0])
-        2'b00: ByteM = ReadDataWordMuxM[7:0];
-        2'b01: ByteM = ReadDataWordMuxM[15:8];
-        2'b10: ByteM = ReadDataWordMuxM[23:16];
-        2'b11: ByteM = ReadDataWordMuxM[31:24];
-      endcase
-    
-      // halfword mux
-      always_comb
-      case(MemPAdrM[1])
-        1'b0: HalfwordM = ReadDataWordMuxM[15:0];
-        1'b1: HalfwordM = ReadDataWordMuxM[31:16];
-      endcase
-
-      // sign extension
-      always_comb
-      case({Funct3M[2], Funct3M[1:0]}) 
-        3'b000:  ReadDataM = {{24{ByteM[7]}}, ByteM};                  // lb
-        3'b001:  ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]};   // lh 
-        3'b010:  ReadDataM = ReadDataWordMuxM;                                   // lw
-        3'b100:  ReadDataM = {24'b0, ByteM[7:0]};                      // lbu
-        3'b101:  ReadDataM = {16'b0, HalfwordM[15:0]};                 // lhu
-        default: ReadDataM = ReadDataWordMuxM;
-      endcase
- -----/\----- EXCLUDED -----/\----- */
     end
   endgenerate
 endmodule
diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv
index 56cc21e9..35dc6f65 100644
--- a/wally-pipelined/src/privileged/csrc.sv
+++ b/wally-pipelined/src/privileged/csrc.sv
@@ -93,13 +93,9 @@ module csrc #(parameter
   generate
     if (`ZICOUNTERS_SUPPORTED) begin
       logic [63:0] CYCLE_REGW, INSTRET_REGW;
-      logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired
-      logic [63:0] CYCLEPlusM, INSTRETPlusM;
-      logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM;
-      logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
-      logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M;
+     logic [63:0] CYCLEPlusM, INSTRETPlusM;
+       logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
       logic        WriteCYCLEM, WriteINSTRETM;
-      logic        WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
       logic [4:0]  CounterNumM;
       logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW;
       logic 			       InstrValidNotFlushedM;