forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
c2f340681d
@ -1,3 +1,3 @@
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vsim -c <<!
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do wally-busybear.do
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do wally-busybear-batch.do
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!
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46
wally-pipelined/regression/wally-busybear-batch.do
Normal file
46
wally-pipelined/regression/wally-busybear-batch.do
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@ -0,0 +1,46 @@
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# wally-pipelined.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with testbench_busybear
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-pipelined.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-pipelined.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work-busybear] {
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vdel -all -lib work-busybear
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}
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vlib work-busybear
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc=+/testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench_busybear -o workopt
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vsim workopt -suppress 8852,12070
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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run -all
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quit
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@ -42,15 +42,6 @@ switch $argc {
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM
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mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
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mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
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mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
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mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/dtim/RAM
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mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/dtim/RAM
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mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM
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mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM
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view wave
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@ -63,7 +54,9 @@ add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/hart/ifu/PCF
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
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add wave -hex /testbench_busybear/dut/InstrF
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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add wave /testbench_busybear/CheckInstrF
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add wave /testbench_busybear/lastCheckInstrF
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add wave /testbench_busybear/speculative
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@ -95,6 +95,14 @@ module testbench_busybear();
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end
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end
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// initial loading of memories
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initial begin
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$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
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$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM);
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$readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3);
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$readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM);
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end
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integer warningCount = 0;
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//logic[63:0] adrTranslation[4:0];
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@ -154,10 +162,10 @@ module testbench_busybear();
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$display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
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force dut.hart.ieu.dp.regf.rf[i] = regExpected;
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release dut.hart.ieu.dp.regf.rf[i];
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end
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//if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin
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// force dut.hart.ieu.dp.regf.rf[i] = regExpected;
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// release dut.hart.ieu.dp.regf.rf[i];
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//end
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end
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end
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end
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@ -179,8 +187,8 @@ module testbench_busybear();
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logic [`XLEN-1:0] readAdrExpected;
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always @(dut.hart.MemRWM[1] or HADDR) begin
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if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin
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always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin
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if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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`ERROR
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@ -194,7 +202,7 @@ module testbench_busybear();
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end
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if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
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$display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
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$display("warning %0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE);
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warningCount += 1;
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`ERROR
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end
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@ -340,13 +348,40 @@ module testbench_busybear();
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always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
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if(~HWRITE) begin
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#3;
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if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin
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if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
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if (dut.PCF !== lastPCF) begin
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lastCheckInstrF = CheckInstrF;
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lastPC <= dut.PCF;
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lastPC2 <= lastPC;
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if (speculative && (lastPC != pcExpected)) begin
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speculative = ~equal(dut.PCF,pcExpected,3);
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if(dut.PCF===pcExpected) begin
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if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrF = 32'b0010011;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = 32'b0010011;
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#7;
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release dut.hart.ifu.InstrF;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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warningCount += 1;
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forcedInstr = 1;
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end
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else begin
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if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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release CheckInstrF;
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force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
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#7;
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release dut.hart.ifu.InstrF;
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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warningCount += 1;
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forcedInstr = 1;
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end
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else begin
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forcedInstr = 0;
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end
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end
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end
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end
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else begin
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if($feof(data_file_PC)) begin
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@ -359,15 +394,24 @@ module testbench_busybear();
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PCtext = {PCtext, " ", PCtext2};
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
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if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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CheckInstrF = 32'b0010011;
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$display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF);
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if(dut.PCF === pcExpected) begin
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if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrF = 32'b0010011;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = 32'b0010011;
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#7;
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release dut.hart.ifu.InstrF;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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warningCount += 1;
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forcedInstr = 1;
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end
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else begin
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if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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release CheckInstrF;
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force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
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#7;
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release dut.hart.ifu.InstrF;
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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warningCount += 1;
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forcedInstr = 1;
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@ -376,6 +420,7 @@ module testbench_busybear();
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forcedInstr = 0;
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end
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end
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end
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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