From 93c9c574267dd5b7c5e111c6b74210715fb196a4 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:26:26 +0000 Subject: [PATCH 1/4] busybear: load mem files from verilog instead of .do --- wally-pipelined/regression/wally-busybear.do | 9 --------- wally-pipelined/testbench/testbench-busybear.sv | 8 ++++++++ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 271b8237..7e0fd66b 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -42,15 +42,6 @@ switch $argc { 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} } -mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/bootdtim/RAM -mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM -mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram -mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram -mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/dtim/RAM -mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/dtim/RAM -mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM -mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM - view wave diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index e6ba95a1..ba554e53 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -95,6 +95,14 @@ module testbench_busybear(); end end + // initial loading of memories + initial begin + $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3); + $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.uncore.dtim.RAM); + $readmemh("/courses/e190ax/busybear_boot/bootmem.txt", dut.imem.bootram, 'h1000 >> 3); + $readmemh("/courses/e190ax/busybear_boot/ram.txt", dut.imem.RAM); + end + integer warningCount = 0; //logic[63:0] adrTranslation[4:0]; From 1b206d5a3ce0c2875baf7e0091cdad6480de4a91 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:35:00 +0000 Subject: [PATCH 2/4] busybear: make a second .do file with better optimization for command line mode --- wally-pipelined/regression/sim-busybear-batch | 2 +- .../regression/wally-busybear-batch.do | 46 +++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 wally-pipelined/regression/wally-busybear-batch.do diff --git a/wally-pipelined/regression/sim-busybear-batch b/wally-pipelined/regression/sim-busybear-batch index 2c351aad..194863b4 100755 --- a/wally-pipelined/regression/sim-busybear-batch +++ b/wally-pipelined/regression/sim-busybear-batch @@ -1,3 +1,3 @@ vsim -c <" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work-busybear] { + vdel -all -lib work-busybear +} +vlib work-busybear + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt +vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 + + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc=+/testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench_busybear -o workopt + +vsim workopt -suppress 8852,12070 +# load the branch predictors with known data. The value of the data is not important for function, but +# is important for perventing pessimistic x propagation. +mem load -infile twoBitPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/DirPredictor/memory/memory +switch $argc { + 0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} + 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} +} + +run -all +quit From c780a25f926ffc6e99057cf5be7dfc8f055792bf Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 19:48:12 +0000 Subject: [PATCH 3/4] busybear: better instrF checking So this now checks instrF only when StallD is low. @kaveh I'd love your opinion on this. I don't know if this is a good idea or not. Ideally we should probably be checking InstrRawD instead, but I kind of want to stay checking the instr in the F stage instead of D for now. Idk if this is worth staying in F, I can't really see any big downsides to checking the instruction in D except that PCD isn't an external signal, but neither is StallD, so..... Anyway I'd love others' thoughts on this --- wally-pipelined/regression/wally-busybear.do | 190 +++++++++--------- .../testbench/testbench-busybear.sv | 10 +- 2 files changed, 101 insertions(+), 99 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 7e0fd66b..42d04cb7 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -1,37 +1,37 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with testbench_busybear -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-busybear] { - vdel -all -lib work-busybear -} -vlib work-busybear - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with testbench_busybear +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work-busybear] { + vdel -all -lib work-busybear +} +vlib work-busybear + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench_busybear -o workopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc work.testbench_busybear -o workopt vsim workopt -suppress 8852,12070 # load the branch predictors with known data. The value of the data is not important for function, but @@ -42,31 +42,33 @@ switch $argc { 1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench_busybear/dut/hart/ifu/bpred/TargetPredictor/memory/memory} } - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave /testbench_busybear/clk -add wave /testbench_busybear/reset -add wave -divider + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave /testbench_busybear/clk +add wave /testbench_busybear/reset +add wave -divider add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/pcExpected -add wave -hex /testbench_busybear/dut/hart/ifu/PCF -add wave -hex /testbench_busybear/dut/hart/ifu/InstrF -add wave -hex /testbench_busybear/dut/InstrF +add wave -hex /testbench_busybear/dut/hart/ifu/PCF +add wave -hex /testbench_busybear/dut/hart/ifu/InstrF +add wave -hex /testbench_busybear/dut/hart/ifu/StallD +add wave -hex /testbench_busybear/dut/hart/ifu/FlushD +add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD add wave /testbench_busybear/CheckInstrF add wave /testbench_busybear/lastCheckInstrF add wave /testbench_busybear/speculative add wave /testbench_busybear/lastPC2 -add wave -divider -add wave -divider +add wave -divider +add wave -divider add wave /testbench_busybear/dut/uncore/HSELBootTim add wave /testbench_busybear/dut/uncore/HSELTim add wave /testbench_busybear/dut/uncore/HREADTim add wave /testbench_busybear/dut/uncore/dtim/HREADTim0 add wave /testbench_busybear/dut/uncore/HREADYTim -add wave -divider +add wave -divider add wave /testbench_busybear/dut/uncore/HREADBootTim add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0 add wave /testbench_busybear/dut/uncore/HREADYBootTim @@ -80,8 +82,8 @@ add wave /testbench_busybear/dut/uncore/HRDATA #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG -add wave -divider -# registers! +add wave -divider +# registers! add wave -hex /testbench_busybear/regExpected add wave -hex /testbench_busybear/regNumExpected add wave -hex /testbench_busybear/HWRITE @@ -121,49 +123,49 @@ add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31] -add wave /testbench_busybear/InstrFName -add wave -hex /testbench_busybear/dut/hart/ifu/PCD -#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD -add wave /testbench_busybear/InstrDName -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCE -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE -add wave /testbench_busybear/InstrEName -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE -add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE -#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCM -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM -add wave /testbench_busybear/InstrMName -#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite -#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM -#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM -#add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCW -##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW -add wave /testbench_busybear/InstrWName -#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW -#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW -#add wave -divider -##add ww -add wave -hex -r /testbench_busybear/* -# -#-- Set Wave Output Items -#TreeUpdate [SetDefaultTree] -#WaveRestoreZoom {0 ps} {100 ps} -#configure wave -namecolwidth 250 -#configure wave -valuecolwidth 120 -#configure wave -justifyvalue left -#configure wave -signalnamewidth 0 -#configure wave -snapdistance 10 -#configure wave -datasetprefix 0 -#configure wave -rowmargin 4 -#configure wave -childrowmargin 2 -#set DefaultRadix hexadecimal -# -#-- Run the Simulation -run -all -##quit +add wave /testbench_busybear/InstrFName +add wave -hex /testbench_busybear/dut/hart/ifu/PCD +#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD +add wave /testbench_busybear/InstrDName +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCE +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE +add wave /testbench_busybear/InstrEName +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE +add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE +#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCM +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM +add wave /testbench_busybear/InstrMName +#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite +#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM +#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM +#add wave -divider +add wave -hex /testbench_busybear/dut/hart/ifu/PCW +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW +add wave /testbench_busybear/InstrWName +#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW +#add wave -divider +##add ww +add wave -hex -r /testbench_busybear/* +# +#-- Set Wave Output Items +#TreeUpdate [SetDefaultTree] +#WaveRestoreZoom {0 ps} {100 ps} +#configure wave -namecolwidth 250 +#configure wave -valuecolwidth 120 +#configure wave -justifyvalue left +#configure wave -signalnamewidth 0 +#configure wave -snapdistance 10 +#configure wave -datasetprefix 0 +#configure wave -rowmargin 4 +#configure wave -childrowmargin 2 +#set DefaultRadix hexadecimal +# +#-- Run the Simulation +run -all +##quit diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index ba554e53..6b54abf6 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -162,10 +162,10 @@ module testbench_busybear(); $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end - if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin - force dut.hart.ieu.dp.regf.rf[i] = regExpected; - release dut.hart.ieu.dp.regf.rf[i]; - end + //if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin + // force dut.hart.ieu.dp.regf.rf[i] = regExpected; + // release dut.hart.ieu.dp.regf.rf[i]; + //end end end end @@ -348,7 +348,7 @@ module testbench_busybear(); always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin if(~HWRITE) begin #3; - if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin + if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin if (dut.PCF !== lastPCF) begin lastCheckInstrF = CheckInstrF; lastPC <= dut.PCF; From 4a8b689f622f89c2d12a83b2aa7382c249f33fb2 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Mon, 8 Mar 2021 21:24:19 +0000 Subject: [PATCH 4/4] busybear: better NOPing out of float instructions --- .../testbench/testbench-busybear.sv | 65 +++++++++++++++---- 1 file changed, 51 insertions(+), 14 deletions(-) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 6b54abf6..e4c9c9e3 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -187,8 +187,8 @@ module testbench_busybear(); logic [`XLEN-1:0] readAdrExpected; - always @(dut.hart.MemRWM[1] or HADDR) begin - if (dut.hart.MemRWM[1] && HADDR != dut.PCF) begin + always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin + if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin if($feof(data_file_memR)) begin $display("no more memR data to read"); `ERROR @@ -202,7 +202,7 @@ module testbench_busybear(); end if (((readMask & HRDATA) !== (readMask & dut.HRDATA)) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin - $display("warning %0t ps, instr %0d: HRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); + $display("warning %0t ps, instr %0d: ExpectedHRDATA does not equal dut.HRDATA: %x, %x from address %x, %x", $time, instrs, HRDATA, dut.HRDATA, HADDR, HSIZE); warningCount += 1; `ERROR end @@ -355,6 +355,33 @@ module testbench_busybear(); lastPC2 <= lastPC; if (speculative && (lastPC != pcExpected)) begin speculative = ~equal(dut.PCF,pcExpected,3); + if(dut.PCF===pcExpected) begin + if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs + force CheckInstrF = 32'b0010011; + release CheckInstrF; + force dut.hart.ifu.InstrF = 32'b0010011; + #7; + release dut.hart.ifu.InstrF; + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); + warningCount += 1; + forcedInstr = 1; + end + else begin + if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD + force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; + release CheckInstrF; + force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; + #7; + release dut.hart.ifu.InstrF; + $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + warningCount += 1; + forcedInstr = 1; + end + else begin + forcedInstr = 0; + end + end + end end else begin if($feof(data_file_PC)) begin @@ -367,21 +394,31 @@ module testbench_busybear(); PCtext = {PCtext, " ", PCtext2}; end scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF); - if(CheckInstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs - CheckInstrF = 32'b0010011; - $display("warning: NOPing out %s at PC=%0x", PCtext, dut.PCF); - warningCount += 1; - forcedInstr = 1; - end - else begin - if(CheckInstrF[28:27] != 2'b11 && CheckInstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD - CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; - $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + if(dut.PCF === pcExpected) begin + if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs + force CheckInstrF = 32'b0010011; + release CheckInstrF; + force dut.hart.ifu.InstrF = 32'b0010011; + #7; + release dut.hart.ifu.InstrF; + $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); warningCount += 1; forcedInstr = 1; end else begin - forcedInstr = 0; + if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD + force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; + release CheckInstrF; + force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; + #7; + release dut.hart.ifu.InstrF; + $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); + warningCount += 1; + forcedInstr = 1; + end + else begin + forcedInstr = 0; + end end end // then expected PC value