forked from Github_Repos/cvw
Division cleanup
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@ -54,21 +54,21 @@ module fdivsqrtpreproc (
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator
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logic [`DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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logic signedDiv; // signed division
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logic NegQuotE; // Integer quotient is negative
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logic AsE, BsE; // Signs of integer inputs
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logic [`XLEN-1:0] AE; // input A after W64 adjustment
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if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
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logic signedDiv, NegQuotE;
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logic AsE, BsE, ALTBE;
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logic [`XLEN-1:0] AE, BE, PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, p;
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logic [`XLEN-1:0] BE, PosA, PosB;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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assign NegQuotE = AsE ^ BsE; // Quotient is negative
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// Source handling
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if (`XLEN==64) begin // 64-bit, supports W64
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mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE);
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@ -81,14 +81,40 @@ module fdivsqrtpreproc (
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assign BZeroE = ~(|BE);
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assign AsE = AE[`XLEN-1] & signedDiv;
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assign BsE = BE[`XLEN-1] & signedDiv;
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assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative
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// Force integer inputs to be postiive
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mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
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mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
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// Select integer or floating point inputs
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mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenX);
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mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenD);
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mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFX);
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mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFD);
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end else begin // Int not supported
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assign IFX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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end
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// count leading zeros for Subnorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFX, ell);
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lzc #(`DIVb) lzcY (IFD, mE);
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// Normalization shift
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assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
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assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for normal inputs)
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// shift square root to be in range [1/4, 1)
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// Normalized numbers are shifted right by 1 if the exponent is odd
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
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logic [`DIVBLEN:0] ZeroDiff, p;
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logic ALTBE;
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// calculate number of fractional bits p
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assign ZeroDiff = mE - ell; // Difference in number of leading zeros
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@ -127,34 +153,16 @@ module fdivsqrtpreproc (
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flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
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if (`XLEN==64)
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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end else begin // Int not supported
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assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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end else begin
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assign NumerZeroE = XZeroE;
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assign X = PreShiftX;
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end
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// count leading zeros for Subnorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFNormLenX, ell);
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lzc #(`DIVb) lzcY (IFNormLenD, mE);
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// Normalization shift
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for normal inputs)
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// shift square root to be in range [1/4, 1)
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// Normalized numbers are shifted right by 1 if the exponent is odd
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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