Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fixed backward mux in fdivsqrtstage2

Browse Source
This commit is contained in:
David Harris 2022-12-31 06:55:20 -08:00
parent 7c7d40ad63
commit c1689b54bb
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
View File

@ -68,12 +68,11 @@ module fdivsqrtstage2 (
always_comb always_comb
if (up) Dsel = DBar; if (up) Dsel = DBar;
else if (uz) Dsel = '0; else if (uz) Dsel = '0;
else Dsel = {3'b000, 1'b1, D}; // un else Dsel = {4'b0001, D}; // un
// Partial Product Generation // Partial Product Generation
// WSA, WCA = WS + WC - qD // WSA, WCA = WS + WC - qD
mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn); mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
//assign AddIn = SqrtE ? F : Dsel;
csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA); csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
assign WSNext = WSA << 1; assign WSNext = WSA << 1;
assign WCNext = WCA << 1; assign WCNext = WCA << 1;