forked from Github_Repos/cvw
Fixed backward mux in fdivsqrtstage2
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@ -68,12 +68,11 @@ module fdivsqrtstage2 (
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always_comb
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always_comb
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if (up) Dsel = DBar;
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if (up) Dsel = DBar;
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else if (uz) Dsel = '0;
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else if (uz) Dsel = '0;
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else Dsel = {3'b000, 1'b1, D}; // un
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else Dsel = {4'b0001, D}; // un
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// Partial Product Generation
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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// WSA, WCA = WS + WC - qD
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mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn);
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mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
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//assign AddIn = SqrtE ? F : Dsel;
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csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
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csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
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assign WSNext = WSA << 1;
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assign WSNext = WSA << 1;
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assign WCNext = WCA << 1;
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assign WCNext = WCA << 1;
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