From c1689b54bbc7ab04bf0de573b67e1eecf0bc9465 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 31 Dec 2022 06:55:20 -0800
Subject: [PATCH] Fixed backward mux in fdivsqrtstage2

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index 857aa411..cfbf951f 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -68,12 +68,11 @@ module fdivsqrtstage2 (
   always_comb
     if      (up) Dsel = DBar;
     else if (uz) Dsel = '0;
-    else         Dsel = {3'b000, 1'b1, D}; // un
+    else         Dsel = {4'b0001, D}; // un
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
-  mux2 #(`DIVb+4) addinmux(F, Dsel, SqrtE, AddIn);
-  //assign AddIn = SqrtE ? F : Dsel;
+  mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
   csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
   assign WSNext = WSA << 1;
   assign WCNext = WCA << 1;