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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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bbracker 2021-07-04 17:15:40 -04:00
commit c110fffe69
14 changed files with 145 additions and 164 deletions
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3
wally-pipelined/src/ifu/ifu.sv
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@ -70,7 +70,8 @@ module ifu (
input logic [`XLEN-1:0] PageTableEntryF,
input logic [1:0] PageTypeF,
input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
input logic ITLBWriteF, ITLBFlushF,
input logic WalkerInstrPageFaultF,

3
wally-pipelined/src/lsu/lsu.sv
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@ -75,7 +75,8 @@ module lsu (
input logic [`XLEN-1:0] PageTableEntryM,
input logic [1:0] PageTypeM,
input logic [`XLEN-1:0] SATP_REGW, // from csr
input logic STATUS_MXR, STATUS_SUM, // from csr
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
input logic DTLBWriteM,
output logic DTLBMissM,
input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.

3
wally-pipelined/src/mmu/mmu.sv
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@ -34,7 +34,8 @@ module mmu #(parameter ENTRY_BITS = 3,
input logic clk, reset,
// Current value of satp CSR (from privileged unit)
input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
// Current privilege level of the processeor
input logic [1:0] PrivilegeModeW,

75
wally-pipelined/src/mmu/tlb.sv
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@ -55,7 +55,8 @@ module tlb #(parameter ENTRY_BITS = 3,
// Current value of satp CSR (from privileged unit)
input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP,
// Current privilege level of the processeor
input logic [1:0] PrivilegeModeW,
@ -87,20 +88,23 @@ module tlb #(parameter ENTRY_BITS = 3,
output logic TLBPageFault
);
localparam NENTRIES = 2**ENTRY_BITS;
logic Translate;
logic TLBAccess, ReadAccess, WriteAccess;
// Store current virtual memory mode (SV32, SV39, SV48, ect...)
logic [`SVMODE_BITS-1:0] SvMode;
logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
// Index (currently random) to write the next TLB entry
logic [ENTRY_BITS-1:0] WriteIndex;
logic [(2**ENTRY_BITS)-1:0] WriteLines, WriteEnables; // used as the one-hot encoding of WriteIndex
//logic [ENTRY_BITS-1:0] WriteIndex;
logic [NENTRIES-1:0] ReadLines, WriteLines, WriteEnables; // used as the one-hot encoding of WriteIndex
// Sections of the virtual and physical addresses
logic [`VPN_BITS-1:0] VirtualPageNumber;
logic [`PPN_BITS-1:0] PhysicalPageNumber, PhysicalPageNumberMixed;
logic [`PA_BITS-1:0] PhysicalAddressFull;
logic [`XLEN+1:0] VAExt;
// Sections of the page table entry
logic [7:0] PTEAccessBits;
@ -110,17 +114,19 @@ module tlb #(parameter ENTRY_BITS = 3,
logic PTE_U, PTE_X, PTE_W, PTE_R;
// Pattern location in the CAM and type of page hit
logic [ENTRY_BITS-1:0] VPNIndex;
//ogic [ENTRY_BITS-1:0] VPNIndex;
logic [1:0] HitPageType;
// Whether the virtual address has a match in the CAM
logic CAMHit;
// Grab the sv mode from SATP
// Grab the sv mode from SATP and determine whether translation should occur
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign Translate = (SvMode != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~ DisableTranslation;
// Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
//decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
assign WriteEnables = WriteLines & {(2**ENTRY_BITS){TLBWrite}};
// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
@ -136,79 +142,64 @@ module tlb #(parameter ENTRY_BITS = 3,
end
endgenerate
// Whether translation should occur
assign Translate = (SvMode != `NO_TRANSLATE) & (PrivilegeModeW != `M_MODE) & ~ DisableTranslation;
// Determine how the TLB is currently being used
// Note that we use ReadAccess for both loads and instruction fetches
assign ReadAccess = TLBAccessType[1];
assign WriteAccess = TLBAccessType[0];
assign TLBAccess = ReadAccess || WriteAccess;
assign PageOffset = VirtualAddress[11:0];
// TLB entries are evicted according to the LRU algorithm
tlblru #(ENTRY_BITS) lru(.*);
// TLB memory
tlbram #(ENTRY_BITS) tlbram(.*);
tlbcam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
// unswizzle useful PTE bits
assign PTE_U = PTEAccessBits[4];
assign PTE_X = PTEAccessBits[3];
assign PTE_W = PTEAccessBits[2];
assign PTE_R = PTEAccessBits[1];
// Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced.
// For superpages, some segments are considered offsets into a larger page.
tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed);
// unswizzle useful PTE bits
assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1];
// Check whether the access is allowed, page faulting if not.
// *** We might not have S mode.
generate
if (ITLB == 1) begin
logic ImproperPrivilege;
// User mode may only execute user mode pages, and supervisor mode may
// only execute non-user mode pages.
assign ImproperPrivilege = ((PrivilegeModeW == `U_MODE) && ~PTE_U) ||
((PrivilegeModeW == `S_MODE) && PTE_U);
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
((EffectivePrivilegeMode == `S_MODE) && PTE_U);
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X);
end else begin
logic ImproperPrivilege, InvalidRead, InvalidWrite;
// User mode may only load/store from user mode pages, and supervisor mode
// may only access user mode pages when STATUS_SUM is low.
assign ImproperPrivilege = ((PrivilegeModeW == `U_MODE) && ~PTE_U) ||
((PrivilegeModeW == `S_MODE) && PTE_U && ~STATUS_SUM);
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) && ~PTE_U) ||
((EffectivePrivilegeMode == `S_MODE) && PTE_U && ~STATUS_SUM);
// Check for read error. Reads are invalid when the page is not readable
// (and executable pages are not readable) or when the page is neither
// readable nor executable (and executable pages are readable).
assign InvalidRead = ReadAccess &&
((~STATUS_MXR && ~PTE_R) || (STATUS_MXR && ~PTE_R && PTE_X));
assign InvalidRead = ReadAccess && ~PTE_R && (~STATUS_MXR | ~PTE_X);
// Check for write error. Writes are invalid when the page's write bit is
// low.
assign InvalidWrite = WriteAccess && ~PTE_W;
assign TLBPageFault = Translate && TLBHit &&
(ImproperPrivilege || InvalidRead || InvalidWrite);
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || InvalidRead || InvalidWrite);
end
endgenerate
// Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced.
// For superpages, some segments are considered offsets into a larger page.
physicalpagemask PageNumberMixer(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed);
// Provide physical address only on TLBHits to cause catastrophic errors if
// garbage address is used.
assign PhysicalAddressFull = (TLBHit) ?
{PhysicalPageNumberMixed, PageOffset} : '0;
// Output the hit physical address if translation is currently on.
generate
if (`XLEN == 32) begin
mux2 #(`PA_BITS) addressmux({2'b0, VirtualAddress}, PhysicalAddressFull, Translate, PhysicalAddress);
end else begin
mux2 #(`PA_BITS) addressmux(VirtualAddress[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress);
end
endgenerate
// Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
assign VAExt = {2'b00, VirtualAddress}; // extend length of virtual address if necessary for RV32
assign PageOffset = VirtualAddress[11:0];
assign PhysicalAddressFull = TLBHit ? {PhysicalPageNumberMixed, PageOffset} : '0;
mux2 #(`PA_BITS) addressmux(VAExt[`PA_BITS-1:0], PhysicalAddressFull, Translate, PhysicalAddress);
assign TLBHit = CAMHit & TLBAccess;
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;

36
wally-pipelined/src/mmu/tlbcam.sv
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@ -34,20 +34,18 @@ module tlbcam #(parameter ENTRY_BITS = 3,
input logic clk, reset,
input logic [KEY_BITS-1:0] VirtualPageNumber,
input logic [1:0] PageTypeWriteVal,
// input logic [`SVMODE_BITS-1:0] SvMode, // *** may not need to be used.
// input logic TLBWrite,
input logic TLBFlush,
input logic [2**ENTRY_BITS-1:0] WriteEnables,
output logic [ENTRY_BITS-1:0] VPNIndex,
//output logic [ENTRY_BITS-1:0] VPNIndex,
output logic [2**ENTRY_BITS-1:0] ReadLines,
output logic [1:0] HitPageType,
output logic CAMHit
);
localparam NENTRIES = 2**ENTRY_BITS;
logic [1:0] PageTypeList [NENTRIES-1:0];
logic [1:0] PageTypeRead [NENTRIES-1:0];
logic [NENTRIES-1:0] Matches;
// Create NENTRIES CAM lines, each of which will independently consider
@ -56,30 +54,18 @@ module tlbcam #(parameter ENTRY_BITS = 3,
// of page type. However, matches are determined based on a subset of the
// page number segments.
camline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
.CAMLineWrite(WriteEnables),
.PageType(PageTypeList),
.Match(Matches),
.*);
/*
generate
genvar i;
for (i = 0; i < NENTRIES; i++) begin
camline #(KEY_BITS, SEGMENT_BITS) camline(
.CAMLineWrite(WriteEnables[i]),
.PageType(PageTypeList[i]),
.Match(Matches[i]),
.*);
end
endgenerate
*/
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[NENTRIES-1:0](
.WriteEnable(WriteEnables),
.PageTypeRead, // *** change name to agree
.Match(ReadLines), // *** change name to agree
.*);
// In case there are multiple matches in the CAM, select only one
// *** it might be guaranteed that the CAM will never have multiple matches.
// If so, this is just an encoder
priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
//priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
assign CAMHit = |Matches & ~TLBFlush;
assign HitPageType = PageTypeList[VPNIndex];
assign CAMHit = |ReadLines & ~TLBFlush;
assign HitPageType = PageTypeRead.or; // applies OR to elements of the (NENTRIES x 2) array to get 2-bit result
endmodule

24
wally-pipelined/src/mmu/camline.sv → wally-pipelined/src/mmu/tlbcamline.sv
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////
// camline.sv
// tlbcamline.sv
//
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021
// Modified: kmacsaigoren@hmc.edu 1 June 2021
@ -28,7 +28,7 @@
`include "wally-config.vh"
module camline #(parameter KEY_BITS = 20,
module tlbcamline #(parameter KEY_BITS = 20,
parameter SEGMENT_BITS = 10) (
input logic clk, reset,
@ -39,7 +39,7 @@ module camline #(parameter KEY_BITS = 20,
input logic [KEY_BITS-1:0] VirtualPageNumber,
// Signals to write a new entry to this line
input logic CAMLineWrite,
input logic WriteEnable,
input logic [1:0] PageTypeWriteVal,
// Flush this line (set valid to 0)
@ -50,19 +50,21 @@ module camline #(parameter KEY_BITS = 20,
// PageType == 2'b01 --> megapage
// PageType == 2'b10 --> gigapage
// PageType == 2'b11 --> terapage
output logic [1:0] PageType, // *** should this be the stored version or the always updated one?
output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
output logic Match
);
// This entry has KEY_BITS for the key plus one valid bit.
logic Valid;
logic [KEY_BITS-1:0] Key;
logic [1:0] PageType;
// Split up key and query into sections for each page table level.
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
logic Match0, Match1;
// *** need to add ASID and G bit support
generate
if (`XLEN == 32) begin
@ -85,26 +87,26 @@ module camline #(parameter KEY_BITS = 20,
assign {Key3, Key2, Key1, Key0} = Key;
// Calculate the actual match value based on the input vpn and the page type.
// For example, a gigapage in SV only cares about VPN[2], so VPN[0] and VPN[1]
// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
// should automatically match.
assign Match0 = (Query0 == Key0) || (PageType > 2'd0); // least signifcant section
assign Match1 = (Query1 == Key1) || (PageType > 2'd1);
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
assign Match3 = (Query3 == Key3); // *** this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam
assign Match3 = (Query3 == Key3); // this should always match in sv39 since both vPN3 and key3 are zeroed by the pagetable walker before getting to the cam
assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
end
endgenerate
// On a write, update the type of the page referred to by this line.
flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType);
//mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType);
flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType);
assign PageTypeRead = PageType & {2{Match}};
// On a write, set the valid bit high and update the stored key.
// On a flush, zero the valid bit and leave the key unchanged.
// *** Might we want to update stored key right away to output match on the
// write cycle? (using a mux)
flopenrc #(1) validbitflop(clk, reset, TLBFlush, CAMLineWrite, 1'b1, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, CAMLineWrite, VirtualPageNumber, Key);
flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, VirtualPageNumber, Key);
endmodule

32
wally-pipelined/src/mmu/tlblru.sv
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@ -28,11 +28,9 @@ module tlblru #(parameter ENTRY_BITS = 3) (
input logic clk, reset,
input logic TLBWrite,
input logic TLBFlush,
input logic [ENTRY_BITS-1:0] VPNIndex,
input logic [2**ENTRY_BITS-1:0] ReadLines,
input logic CAMHit,
input logic [2**ENTRY_BITS-1:0] WriteLines,
output logic [ENTRY_BITS-1:0] WriteIndex
output logic [2**ENTRY_BITS-1:0] WriteLines
);
localparam NENTRIES = 2**ENTRY_BITS;
@ -41,29 +39,19 @@ module tlblru #(parameter ENTRY_BITS = 3) (
logic [NENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
// One-hot encodings of which line is being accessed
logic [NENTRIES-1:0] ReadLineOneHot, AccessLineOneHot;
logic [NENTRIES-1:0] AccessLines;
// High if the next access causes all RU bits to be 1
logic AllUsed;
// Convert indices to one-hot encodings
decoder #(ENTRY_BITS) readdecoder(VPNIndex, ReadLineOneHot);
// Find the first line not recently used
priorityencoder #(ENTRY_BITS) firstnru(~RUBits, WriteIndex);
tlbpriority #(NENTRIES) nru(~RUBits, WriteLines);
// Access either the hit line or written line
assign AccessLineOneHot = (TLBWrite) ? WriteLines : ReadLineOneHot;
// Raise the bit of the recently accessed line
assign RUBitsAccessed = AccessLineOneHot | RUBits;
// Determine whether we need to reset the RU bits to all zeroes
assign AllUsed = &(RUBitsAccessed);
assign RUBitsNext = (AllUsed) ? AccessLineOneHot : RUBitsAccessed;
// Update LRU state on any TLB hit or write
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite),
RUBitsNext, RUBits);
// Track recently used lines, updating on a CAM Hit or TLB write
assign AccessLines = TLBWrite ? WriteLines : ReadLines;
assign RUBitsAccessed = AccessLines | RUBits;
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
flopenrc #(NENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit || TLBWrite), RUBitsNext, RUBits);
endmodule

11
wally-pipelined/src/mmu/physicalpagemask.sv → wally-pipelined/src/mmu/tlbphysicalpagemask.sv
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////
// physicalpagemask.sv
// tlbphysicalpagemask.sv
//
// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021
// Modified:
@ -28,7 +28,7 @@
`include "wally-config.vh"
module physicalpagemask (
module tlbphysicalpagemask (
input logic [`VPN_BITS-1:0] VPN,
input logic [`PPN_BITS-1:0] PPN,
input logic [1:0] PageType,
@ -40,13 +40,11 @@ module physicalpagemask (
logic [`PPN_BITS-1:0] ZeroExtendedVPN;
logic [`PPN_BITS-1:0] PageNumberMask;
assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
generate
if (`XLEN == 32) begin
always_comb
case (PageType[0])
// *** the widths of these constansts are hardocded here to match `PPN_BITS in the wally-constants file.
// the widths of these constansts are hardocded here to match `PPN_BITS in the wally-constants file.
0: PageNumberMask = 22'h3FFFFF; // kilopage: 22 bits of PPN, 0 bits of VPN
1: PageNumberMask = 22'h3FFC00; // megapage: 12 bits of PPN, 10 bits of VPN
endcase
@ -57,7 +55,7 @@ module physicalpagemask (
1: PageNumberMask = 44'hFFFFFFFFE00; // megapage: 35 bits of PPN, 9 bits of VPN
2: PageNumberMask = 44'hFFFFFFC0000; // gigapage: 26 bits of PPN, 18 bits of VPN
3: PageNumberMask = 44'hFFFF8000000; // terapage: 17 bits of PPN, 27 bits of VPN
// *** make sure that this doesnt break when using sv39. In that case, all of these
// Bus widths accomodate SV48. In SV39, all of these
// busses are the widths for sv48, but extra bits should be zeroed out by the mux
// in the tlb when it generates VPN from the full virtualadress.
endcase
@ -65,6 +63,7 @@ module physicalpagemask (
endgenerate
// merge low segments of VPN with high segments of PPN decided by the pagetype.
assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
assign MixedPageNumber = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
endmodule

50
wally-pipelined/src/mmu/priorityencoder.sv → wally-pipelined/src/mmu/tlbpriority.sv
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@ -1,16 +1,15 @@
///////////////////////////////////////////
// priorityencoder.sv
// tlbpriority.sv
//
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021
// Based on implementation from https://www.allaboutcircuits.com/ip-cores/communication-controller/priority-encoder/
// *** Give proper LGPL attribution for above source
// Modified: Teo Ene 15 Apr 2021:
// Temporarily removed paramterized priority encoder for non-parameterized one
// To get synthesis working quickly
// Kmacsaigoren@hmc.edu 28 May 2021:
// Added working version of parameterized priority encoder.
// David_Harris@Hmc.edu switched to one-hot output
//
// Purpose: One-hot encoding to binary encoder
// Purpose: Priority circuit to choose most significant one-hot output
//
// A component of the Wally configurable RISC-V project.
//
@ -31,35 +30,20 @@
`include "wally-config.vh"
module priorityencoder #(parameter BINARY_BITS = 3) (
input logic [2**BINARY_BITS - 1:0] onehot,
output logic [BINARY_BITS - 1:0] binary
module tlbpriority #(parameter ENTRIES = 8) (
input logic [ENTRIES-1:0] a,
output logic [ENTRIES-1:0] y
);
// verilator lint_off UNOPTFLAT
logic [ENTRIES-1:0] nolower;
integer i;
always_comb begin
binary = 0;
for (i = 0; i < 2**BINARY_BITS; i++) begin
// verilator lint_off WIDTH
if (onehot[i]) binary = i; // prioritizes the most significant bit
// verilator lint_on WIDTH
end
end
// *** triple check synthesizability here
// Ideally this mimics the following:
/*
always_comb begin
casex (one_hot)
1xx ... x: binary = BINARY_BITS - 1;
01x ... x: binary = BINARY_BITS - 2;
001 ... x: binary = BINARY_BITS - 3;
{...}
00 ... 1xx: binary = 2;
00 ... 01x: binary = 1;
00 ... 001: binary = 0;
end
*/
// generate thermometer code mask
genvar i;
generate
assign nolower[0] = 1;
for (i=1; i<ENTRIES; i++)
assign nolower[i] = nolower[i-1] & ~a[i-1];
endgenerate
// verilator lint_on UNOPTFLAT
assign y = a & nolower;
endmodule

22
wally-pipelined/src/mmu/tlbram.sv
View File

@ -29,11 +29,11 @@
module tlbram #(parameter ENTRY_BITS = 3) (
input logic clk, reset,
input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
//input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
// input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused?
input logic [`XLEN-1:0] PTEWriteVal,
// input logic TLBWrite,
input logic [2**ENTRY_BITS-1:0] WriteEnables,
input logic [2**ENTRY_BITS-1:0] ReadLines, WriteEnables,
output logic [`PPN_BITS-1:0] PhysicalPageNumber,
output logic [7:0] PTEAccessBits
@ -41,23 +41,13 @@ module tlbram #(parameter ENTRY_BITS = 3) (
localparam NENTRIES = 2**ENTRY_BITS;
logic [`XLEN-1:0] ram [NENTRIES-1:0];
logic [`XLEN-1:0] RamRead[NENTRIES-1:0];
logic [`XLEN-1:0] PageTableEntry;
// Generate a flop for every entry in the RAM
flopenr #(`XLEN) pteflops[NENTRIES-1:0](clk, reset, WriteEnables, PTEWriteVal, ram);
/*
generate
genvar i;
for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops
flopenr #(`XLEN) pteflop(clk, reset, WriteEnables[i],
PTEWriteVal, ram[i]);
end
endgenerate
*/
assign PageTableEntry = ram[VPNIndex];
tlbramline #(`XLEN) tlblineram[NENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
assign PTEAccessBits = PageTableEntry[7:0];
assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
endmodule

38
wally-pipelined/src/mmu/tlbramline.sv Normal file
View File

@ -0,0 +1,38 @@
///////////////////////////////////////////
// tlbramline.sv
//
// Written: David_Harris@hmc.edu 4 July 2021
// Modified:
//
// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module tlbramline #(parameter WIDTH)
(input logic clk, reset,
input logic re, we,
input logic [WIDTH-1:0] d,
output logic [WIDTH-1:0] q);
logic [WIDTH-1:0] line;
flopenr #(`XLEN) pteflop(clk, reset, we, d, line);
assign q = re ? line : 0;
endmodule

3
wally-pipelined/src/privileged/csr.sv
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@ -58,8 +58,7 @@ module csr #(parameter
output logic [`XLEN-1:0] SATP_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
output logic STATUS_MIE, STATUS_SIE,
output logic STATUS_MXR, STATUS_SUM,
output logic STATUS_MPRV,
output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic [4:0] SetFflagsM,

6
wally-pipelined/src/privileged/privileged.sv
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@ -67,7 +67,8 @@ module privileged (
output logic IllegalFPUInstrE,
output logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] SATP_REGW,
output logic STATUS_MXR, STATUS_SUM,
output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
output logic [1:0] STATUS_MPP,
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic [2:0] FRM_REGW
@ -94,8 +95,7 @@ module privileged (
logic MTrapM, STrapM, UTrapM;
logic InterruptM;
logic [1:0] STATUS_MPP;
logic STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it?
logic STATUS_SPP, STATUS_TSR;
logic STATUS_MIE, STATUS_SIE;
logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
logic md, sd;

3
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -112,7 +112,8 @@ module wallypipelinedhart
logic ITLBMissF, ITLBHitF;
logic DTLBMissM, DTLBHitM;
logic [`XLEN-1:0] SATP_REGW;
logic STATUS_MXR, STATUS_SUM;
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
logic [1:0] STATUS_MPP;
logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
logic [1:0] PageTypeF, PageTypeM;