From bf9683f0d247ae85a1cabd2f308534619bf3cab0 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 31 Mar 2022 11:39:37 -0500
Subject: [PATCH] Forced to go back to hard coded preload.

---
 pipelined/src/generic/flop/bram2p1r1w.sv | 49 ++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/flop/bram2p1r1w.sv
index 89fe432a..4ccfa1c1 100644
--- a/pipelined/src/generic/flop/bram2p1r1w.sv
+++ b/pipelined/src/generic/flop/bram2p1r1w.sv
@@ -58,10 +58,59 @@ module bram2p1r1w
   logic [DATA_WIDTH-1:0] 			 RAM [(2**ADDR_WIDTH)-1:0];
   integer 							 i;
 
+/* -----\/----- EXCLUDED -----\/-----
   initial begin
     if(PRELOAD_ENABLED)
 	  $readmemh(PRELOAD_FILE, RAM);
   end
+ -----/\----- EXCLUDED -----/\----- */
+
+  initial begin
+	if(PRELOAD_ENABLED) begin
+      RAM[0] =  64'h94e1819300002197; 
+      RAM[1] =  64'h4281420141014081; 
+      RAM[2] =  64'h4481440143814301; 
+      RAM[3] =  64'h4681460145814501; 
+      RAM[4] =  64'h4881480147814701; 
+      RAM[5] =  64'h4a814a0149814901; 
+      RAM[6] =  64'h4c814c014b814b01; 
+      RAM[7] =  64'h4e814e014d814d01; 
+      RAM[8] =  64'h0110011b4f814f01; 
+      RAM[9] =  64'h059b45011161016e; 
+      RAM[10] = 64'h0004063705fe0010; 
+      RAM[11] = 64'h05a000ef8006061b; 
+      RAM[12] = 64'h0ff003930000100f; 
+      RAM[13] = 64'h4e952e3110060e37; 
+      RAM[14] = 64'hc602829b0053f2b7; 
+      RAM[15] = 64'h2023fe02dfe312fd; 
+      RAM[16] = 64'h829b0053f2b7007e; 
+      RAM[17] = 64'hfe02dfe312fdc602; 
+      RAM[18] = 64'h4de31efd000e2023; 
+      RAM[19] = 64'h059bf1402573fdd0; 
+      RAM[20] = 64'h0000061705e20870; 
+      RAM[21] = 64'h0010029b01260613; 
+      RAM[22] = 64'h11010002806702fe; 
+      RAM[23] = 64'h84b2842ae426e822; 
+      RAM[24] = 64'h892ee04aec064505; 
+      RAM[25] = 64'h06e000ef07e000ef; 
+      RAM[26] = 64'h979334fd02905563; 
+      RAM[27] = 64'h07930177d4930204; 
+      RAM[28] = 64'h4089093394be2004; 
+      RAM[29] = 64'h04138522008905b3; 
+      RAM[30] = 64'h19e3014000ef2004; 
+      RAM[31] = 64'h64a2644260e2fe94; 
+      RAM[32] = 64'h6749808261056902; 
+      RAM[33] = 64'hdfed8b8510472783; 
+      RAM[34] = 64'h2423479110a73823; 
+      RAM[35] = 64'h10472783674910f7; 
+      RAM[36] = 64'h20058693ffed8b89; 
+      RAM[37] = 64'h05a1118737836749; 
+      RAM[38] = 64'hfed59be3fef5bc23; 
+      RAM[39] = 64'h1047278367498082; 
+      RAM[40] = 64'h67c98082dfed8b85; 
+      RAM[41] = 64'h0000808210a7a023;   
+	end
+  end
 
   // Port-A Operation
   always @ (posedge clk) begin