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Disable IFU bus access on TrapM.

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This commit is contained in:
Ross Thompson 2022-10-01 14:54:16 -05:00
parent e6db1c5cf8
commit bc94f4aef1
1 changed files with 4 additions and 2 deletions
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6
pipelined/src/ifu/ifu.sv
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@ -211,8 +211,10 @@ module ifu (
logic ICacheBusAck; logic ICacheBusAck;
logic SelUncachedAdr; logic SelUncachedAdr;
logic [1:0] CacheBusRW, BusRW; logic [1:0] CacheBusRW, BusRW;
logic IgnoreRequest;
assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}; assign IgnoreRequest = ITLBMissF | TrapM;
assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF};
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
@ -248,7 +250,7 @@ module ifu (
assign IFUHADDR = PCPF; assign IFUHADDR = PCPF;
logic CaptureEn; logic CaptureEn;
logic [1:0] BusRW; logic [1:0] BusRW;
assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF}; assign BusRW = IFURWF & ~{ITLBMissF, ITLBMissF} & ~{TrapM, TrapM};
assign IFUHSIZE = 3'b010; assign IFUHSIZE = 3'b010;
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),