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Added comport.setup to remind how to configure com port for xilinx fpga.

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Added load-deadlock.tsm to trigger load operation deadlock.
This commit is contained in:
Ross Thompson 2022-01-25 14:54:38 -06:00
parent acec56c27e
commit bb11f5637c
2 changed files with 40 additions and 0 deletions
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3
fpga/comport.setup Normal file
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sudo chown ross:ross /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1

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fpga/generator/load-deadlock.tsm Normal file
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##################################################
#
# For info on creating trigger state machines:
# 1) In the main Vivado menu bar, select
# Window > Language Templates
# 2) In the Templates window, select
# Debug > Trigger State Machine
# 3) Refer to the entry 'Info' for an overview
# of the trigger state machine language.
#
# More information can be found in this document:
#
# Vivado Design Suite User Guide: Programming
# and Debugging (UG908)
#
##################################################
state state_reset:
if(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
reset_counter $counter0;
goto state_begin_count;
#goto state_trigger;
else
goto state_reset;
endif
state state_begin_count:
if($counter0 == 16'h0264) then
goto state_trigger;
elseif(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
increment_counter $counter0;
goto state_begin_count;
else
goto state_reset;
endif
state state_trigger:
trigger;