diff --git a/fpga/comport.setup b/fpga/comport.setup
new file mode 100644
index 00000000..cb4108b5
--- /dev/null
+++ b/fpga/comport.setup
@@ -0,0 +1,3 @@
+sudo chown ross:ross /dev/ttyUSB1
+stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
+cat /dev/ttyUSB1
diff --git a/fpga/generator/load-deadlock.tsm b/fpga/generator/load-deadlock.tsm
new file mode 100644
index 00000000..0ff066ef
--- /dev/null
+++ b/fpga/generator/load-deadlock.tsm
@@ -0,0 +1,37 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
+        reset_counter $counter0;
+        goto state_begin_count;
+        #goto state_trigger;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if($counter0 == 16'h0264) then
+        goto state_trigger;
+    elseif(wallypipelinedsoc/hart/PCM == 64'hffffffff802719xx) then
+        increment_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_trigger:
+    trigger;