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Coverage improvements in ieu, hazard units

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This commit is contained in:
David Harris 2023-03-31 08:33:46 -07:00
parent 820e3513c7
commit b95730e3a1
6 changed files with 15 additions and 5 deletions
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6
sim/coverage-exclusions-rv64gc.do
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@ -24,8 +24,12 @@
#// and limitations under the License.
#////////////////////////////////////////////////////////////////////////////////////////////////
# This file should be a last resort. It's preferable to put
# // coverage off
# statements inline with the code whenever possible.
# LZA (i<64) statement confuses coverage tool
# This is ugly to exlcude the whole file - is there a better option
# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working
coverage exclude -srcfile lzc.sv

2
src/hazard/hazard.sv
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@ -88,7 +88,9 @@ module hazard (
assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
// Stall each stage for cause or if the next stage is stalled
// coverage off: StallFCause is always 0
assign #1 StallF = StallFCause | StallD;
// coverage on
assign #1 StallD = StallDCause | StallE;
assign #1 StallE = StallECause | StallM;
assign #1 StallM = StallMCause | StallW;

6
src/ieu/bmu/bmuctrl.sv
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@ -101,8 +101,10 @@ module bmuctrl(
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
17'b0110011_0000100_100: if (`XLEN == 32)
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
// // coverage off: This case can't occur in RV64
// 17'b0110011_0000100_100: if (`XLEN == 32)
// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
// // coverage on
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor

2
src/ieu/controller.sv
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@ -264,7 +264,9 @@ module controller(
end else assign sltD = (Funct3D == 3'b010);
// Combine base and bit manipulation signals
// coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
// coverage on
assign RegWriteD = BaseRegWriteD | BRegWriteD;
assign W64D = BaseW64D | BW64D;
assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;

2
src/lsu/lsu.sv
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@ -149,7 +149,7 @@ module lsu (
// MMU include PMP and is needed if any privileged supported
/////////////////////////////////////////////////////////////////////////////////////////////
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
if(`VIRTMEM_SUPPORTED) begin : hptw
hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,