diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index 9905c897..d58e4c51 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -24,8 +24,12 @@
 #// and limitations under the License.
 #////////////////////////////////////////////////////////////////////////////////////////////////
 
+# This file should be a last resort.  It's preferable to put 
+# // coverage off 
+# statements inline with the code whenever possible.
+
 # LZA (i<64) statement confuses coverage tool 
-# This is ugly to exlcude the whole file - is there a better option
+# This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
 coverage exclude -srcfile lzc.sv 
 
 
diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv
index cf3a22c1..bc9f7baa 100644
--- a/src/hazard/hazard.sv
+++ b/src/hazard/hazard.sv
@@ -88,7 +88,9 @@ module hazard (
   assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
 
   // Stall each stage for cause or if the next stage is stalled
+  // coverage off: StallFCause is always 0
   assign #1 StallF = StallFCause | StallD;
+  // coverage on
   assign #1 StallD = StallDCause | StallE;
   assign #1 StallE = StallECause | StallM;
   assign #1 StallM = StallMCause | StallW;
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 90d031a1..0bfbfeb4 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -101,8 +101,10 @@ module bmuctrl(
                                   BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
                                 else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
                                   BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
-        17'b0110011_0000100_100: if (`XLEN == 32)
-                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        // coverage off: This case can't occur in RV64
+//        17'b0110011_0000100_100: if (`XLEN == 32)
+//                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        // coverage on
         17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
         17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
         17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 5d0b7845..2174b96c 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -264,7 +264,9 @@ module controller(
     end else assign sltD = (Funct3D == 3'b010);
 
     // Combine base and bit manipulation signals
+    // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
     assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
+    // coverage on
     assign RegWriteD = BaseRegWriteD | BRegWriteD; 
     assign W64D = BaseW64D | BW64D;
     assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 0b0bc81e..f2e147f0 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -149,7 +149,7 @@ module lsu (
   // MMU include PMP and is needed if any privileged supported
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
+  if(`VIRTMEM_SUPPORTED) begin : hptw
     hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index 688218b7..db142de5 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -202,7 +202,7 @@ module csr #(parameter
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
   assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW)  & InstrValidNotFlushedM;
+  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
   assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;