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added 1 tick delay on tim reads

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bbracker 2021-03-25 02:15:28 -04:00
parent 682050a33b
commit b5fa410e15
1 changed files with 4 additions and 4 deletions
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8
wally-pipelined/src/uncore/dtim.sv
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@ -85,14 +85,14 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
generate
if (`XLEN == 64) begin
always_ff @(posedge HCLK) begin
HWADDR <= A;
HREADTim0 <= RAM[A[31:3]];
HWADDR <= #1 A;
HREADTim0 <= #1 RAM[A[31:3]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA;
end
end else begin
always_ff @(posedge HCLK) begin
HWADDR <= A;
HREADTim0 <= RAM[A[31:2]];
HWADDR <= #1 A;
HREADTim0 <= #1 RAM[A[31:2]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA;
end
end