From b5fa410e151e2dca17e5c6dc630a59f3e8a13e2c Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 02:15:28 -0400 Subject: [PATCH] added 1 tick delay on tim reads --- wally-pipelined/src/uncore/dtim.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index a5c4574e..f96a14fb 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -85,14 +85,14 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( generate if (`XLEN == 64) begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:3]]; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:3]]; if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA; end end else begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:2]]; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:2]]; if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA; end end